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authorChristudasan Devadasan <Christudasan.Devadasan@amd.com>2026-01-07 12:51:56 +0000
committerChristudasan Devadasan <Christudasan.Devadasan@amd.com>2026-01-13 03:50:24 +0000
commitc74c50e647a667b34c47e035964c37be2aec5243 (patch)
tree74347c674b84924f7be2918a6fa38566fbfd2ddf
parent4343cad32c10a45defe7feba63df493d3e18d13a (diff)
downloadllvm-users/cdevadas/putback-ProperlyAlighedRC.tar.gz
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[AMDGPU] Put back ProperlyAlighedRC helper functionsusers/cdevadas/putback-ProperlyAlighedRC
Putting back the functions that are recently deleted as they were found unused. They are needed for implementing subreg reload during RA.
-rw-r--r--llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp22
-rw-r--r--llvm/lib/Target/AMDGPU/SIRegisterInfo.h5
2 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 3efdad628881..4777e06a001f 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3882,6 +3882,28 @@ bool SIRegisterInfo::isProperlyAlignedRC(const TargetRegisterClass &RC) const {
return true;
}
+const TargetRegisterClass *
+SIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const {
+ if (!RC || !ST.needsAlignedVGPRs())
+ return RC;
+
+ unsigned Size = getRegSizeInBits(*RC);
+ if (Size <= 32)
+ return RC;
+
+ if (RC == &AMDGPU::VS_64RegClass)
+ return &AMDGPU::VS_64_Align2RegClass;
+
+ if (isVGPRClass(RC))
+ return getAlignedVGPRClassForBitWidth(Size);
+ if (isAGPRClass(RC))
+ return getAlignedAGPRClassForBitWidth(Size);
+ if (isVectorSuperClass(RC))
+ return getAlignedVectorSuperClassForBitWidth(Size);
+
+ return RC;
+}
+
ArrayRef<MCPhysReg>
SIRegisterInfo::getAllSGPR128(const MachineFunction &MF) const {
return ArrayRef(AMDGPU::SGPR_128RegClass.begin(), ST.getMaxNumSGPRs(MF) / 4);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 2e2916f68f58..4c8e217aa500 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -431,6 +431,11 @@ public:
// the subtarget.
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
+ // Given \p RC returns corresponding aligned register class if required
+ // by the subtarget.
+ const TargetRegisterClass *
+ getProperlyAlignedRC(const TargetRegisterClass *RC) const;
+
/// Return all SGPR128 which satisfy the waves per execution unit requirement
/// of the subtarget.
ArrayRef<MCPhysReg> getAllSGPR128(const MachineFunction &MF) const;