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| author | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2026-01-13 03:48:15 +0000 |
|---|---|---|
| committer | Christudasan Devadasan <Christudasan.Devadasan@amd.com> | 2026-01-13 03:48:15 +0000 |
| commit | 144d8a2877a431949d350fec6ed24139d2859097 (patch) | |
| tree | 94188b91a55011dae880312f551c84efd44567df | |
| parent | 7cae9252823a45e86ea23244129d40b2d7ee1da9 (diff) | |
| download | llvm-users/cdevadas/make-getNumSubRegsForSpillOp-member-function.zip llvm-users/cdevadas/make-getNumSubRegsForSpillOp-member-function.tar.gz llvm-users/cdevadas/make-getNumSubRegsForSpillOp-member-function.tar.bz2 | |
fixed a comment.users/cdevadas/make-getNumSubRegsForSpillOp-member-function
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 1e46fe0..38b40ec 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -1392,7 +1392,7 @@ public: return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; } - /// Return the number of registers spilled/reloaded by the spill opcode. + /// Return the number of registers spilled/reloaded by the spill instruction. unsigned getNumSubRegsForSpillOp(const MachineInstr &MI) const; /// Legalize the \p OpIndex operand of this instruction by inserting |