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authorMatt Arsenault <Matthew.Arsenault@amd.com>2025-06-26 07:54:46 +0900
committerMatt Arsenault <arsenm2@gmail.com>2025-06-26 07:54:46 +0900
commit6b1e20987044753b8be1802f18180a37a7fba856 (patch)
treebc655b9d135c7235c4cd87e55d653e82052ff92b
parent78da9f1295503fcb36a9a61eb961c050d4ea8374 (diff)
downloadllvm-users/arsenm/machine-combiner/fix-dropping-subreg-indexes.zip
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Try to track NewVR subreg through swapusers/arsenm/machine-combiner/fix-dropping-subreg-indexes
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfo.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 906c019..af828f6 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1332,6 +1332,7 @@ void TargetInstrInfo::reassociateOps(
// recycling RegB because the MachineCombiner's computation of the critical
// path requires a new register definition rather than an existing one.
Register NewVR = MRI.createVirtualRegister(RC);
+ unsigned SubRegNewVR = 0;
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
auto [NewRootOpc, NewPrevOpc] = getReassociationOpcodes(Pattern, Root, Prev);
@@ -1407,6 +1408,7 @@ void TargetInstrInfo::reassociateOps(
if (SwapRootOperands) {
std::swap(RegA, NewVR);
+ std::swap(SubRegA, SubRegNewVR);
std::swap(KillA, KillNewVR);
}
@@ -1420,7 +1422,7 @@ void TargetInstrInfo::reassociateOps(
if (Idx == RootFirstOpIdx)
MIB2 = MIB2.addReg(RegA, getKillRegState(KillA), SubRegA);
else if (Idx == RootSecondOpIdx)
- MIB2 = MIB2.addReg(NewVR, getKillRegState(KillNewVR));
+ MIB2 = MIB2.addReg(NewVR, getKillRegState(KillNewVR), SubRegNewVR);
else
MIB2 = MIB2.add(MO);
}