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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-09-17 21:14:02 +0900 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2025-09-20 08:58:39 +0900 |
| commit | dbb3fe7d0bbbd1e6ffd3505c555146f58a3120d5 (patch) | |
| tree | 6a2b0b6a0139d46b10bca05b3be78ee1ae24b0c0 | |
| parent | 99aa6e5d3adc47a1e4c9d8625db8b2dc58aee88c (diff) | |
| download | llvm-users/arsenm/amdgpu/remove-wrapper-tri-getRegClass.zip llvm-users/arsenm/amdgpu/remove-wrapper-tri-getRegClass.tar.gz llvm-users/arsenm/amdgpu/remove-wrapper-tri-getRegClass.tar.bz2 | |
AMDGPU: Remove wrapper around TRI::getRegClassusers/arsenm/amdgpu/remove-wrapper-tri-getRegClass
This shadows the member in the base class, but differs slightly
in behavior. The base method doesn't check for the invalid case.
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 2 |
4 files changed, 7 insertions, 18 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 533c130..2710b98 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -1301,10 +1301,11 @@ void SIFoldOperandsImpl::foldOperand( continue; const int SrcIdx = MovOp == AMDGPU::V_MOV_B16_t16_e64 ? 2 : 1; - const TargetRegisterClass *MovSrcRC = - TRI->getRegClass(TII->getOpRegClassID(MovDesc.operands()[SrcIdx])); - if (MovSrcRC) { + int16_t RegClassID = TII->getOpRegClassID(MovDesc.operands()[SrcIdx]); + if (RegClassID != -1) { + const TargetRegisterClass *MovSrcRC = TRI->getRegClass(RegClassID); + if (UseSubReg) MovSrcRC = TRI->getMatchingSuperRegClass(SrcRC, MovSrcRC, UseSubReg); if (!MRI->constrainRegClass(SrcReg, MovSrcRC)) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 0619032..a368a0d 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -5964,7 +5964,7 @@ SIInstrInfo::getRegClass(const MCInstrDesc &TID, unsigned OpNum, return nullptr; const MCOperandInfo &OpInfo = TID.operands()[OpNum]; int16_t RegClass = getOpRegClassID(OpInfo); - return RI.getRegClass(RegClass); + return RegClass < 0 ? nullptr : RI.getRegClass(RegClass); } const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, @@ -5982,7 +5982,8 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, return RI.getPhysRegBaseClass(Reg); } - return RI.getRegClass(getOpRegClassID(Desc.operands()[OpNo])); + int16_t RegClass = getOpRegClassID(Desc.operands()[OpNo]); + return RegClass < 0 ? nullptr : RI.getRegClass(RegClass); } void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const { diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index b019c98..af7f0cb 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -3897,17 +3897,6 @@ const TargetRegisterClass *SIRegisterInfo::getVGPR64Class() const { : &AMDGPU::VReg_64RegClass; } -// FIXME: This should be deleted -const TargetRegisterClass * -SIRegisterInfo::getRegClass(unsigned RCID) const { - switch ((int)RCID) { - case -1: - return nullptr; - default: - return AMDGPUGenRegisterInfo::getRegClass(RCID); - } -} - // Find reaching register definition MachineInstr *SIRegisterInfo::findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 7b91ba7..813f6bb 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -391,8 +391,6 @@ public: MCRegister getExec() const; - const TargetRegisterClass *getRegClass(unsigned RCID) const; - // Find reaching register definition MachineInstr *findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, |