index
:
riscv-gnu-toolchain/glibc.git
aaribaud/bugzilla/23789/v2
aaribaud/bugzilla/23789/v4
aaribaud/y2038
aaribaud/y2038-submitted-v1
aj/revert-sunrpc
aj/shared-linux-fcntl
akhuettel/tests-libgcc-3
alistair/rv32.next
alistair/rv32.wip
allan/config-files
andros/avx512f-mem
andros/libmvec
andros/pr19654
archlinux/2.18/master
arm/gcs
arm/gcs-v2
arm/ilp32
arm/morello/main
arm/morello/v1
arm/morello/v2
arm/morello/v3
azanella/bz23960-dirent
azanella/bz30558-posix_timer
azanella/bz31664-openat2
azanella/clang
azanella/memory-seal-v5
azanella/mips-hw-fp-round
carlos/dlmopen
carlos/master
cmetcalf/tile-2.15
codonell/c-utf8
codonell/ld-audit
cvs/fedora-2_3-branch
cvs/fedora-2_5-branch
cvs/fedora-branch
cvs/glibc-2-1-branch
cvs/glibc-2-2-branch
cvs/glibc-2_0_x
cvs/glibc-2_10-branch
cvs/glibc-2_3-branch
cvs/glibc-2_5-branch
cvs/glibc-2_6-branch
cvs/glibc-2_7-branch
cvs/glibc-2_8-branch
cvs/glibc-2_9-branch
cvs/master
cvs/sparc-2_0_x-branch
cvs/thomas-posix1996
davem/sparc
dj/malloc
dj/malloc-tcache
fedora/2.10/master
fedora/2.11/master
fedora/2.12/master
fedora/2.13/master
fedora/2.14/master
fedora/2.22/master
fedora/master
fw/bug16145
fw/bug20018-backport
fw/bug21041
fw/bug21242
fw/bug24214
fw/bug24562
fw/bug25097
fw/bug25112
fw/bug25157
fw/bug25225
fw/bug30619
fw/bug31943-with-test
fw/dl-bind-performance
fw/dlopen-nodelete-reloc
fw/elf-fixups
fw/gcc-10-fixes
fw/getdents64
fw/libc-early-init-2
fw/libm-noprivate-2.27
fw/linux-5.2
fw/localedef-utf8
fw/math-split-tests
fw/no-symlinks
fw/nss-declare
fw/resolv-cleanups
fw/syscall-cleanups
fw/tst-gmon
fw/tst-lchmod
fw/tst-mallocfork2
fw/twalk_r-iconv
fw/vfprintf-2
fw/x86-diagnostics
fw/x86-shstk-backtrace
gabriel/powerpc-ieee128-printscan
gentoo/2.18
gentoo/2.19
gentoo/2.20
gentoo/2.21
gentoo/2.22
gentoo/2.23
gentoo/2.24
gentoo/2.25
google/grte/v4-2.19/master
google/grte/v5-2.27/master
google/grte/v6-2.29/master
hjl/2.17/memset
hjl/32bit/2.22
hjl/32bit/master
hjl/cache/master
hjl/cacheinfo/master
hjl/cacheline/ifunc
hjl/cacheline/master
hjl/ctor/release/2.11
hjl/ctor/release/2.12
hjl/erms/2.22
hjl/erms/2.23
hjl/erms/i386
hjl/erms/ifunc
hjl/erms/master
hjl/erms/nt
hjl/fma/2.26
hjl/fma/master
hjl/global
hjl/gmp
hjl/hwcap/master
hjl/i386/master
hjl/i486/multiarch
hjl/i486/multiarch-old
hjl/implies
hjl/init
hjl/ld.so/master
hjl/memcpy/dpdk/master
hjl/mempcpy
hjl/nsz/math
hjl/plt/2.21
hjl/plt/2.22
hjl/plt/master
hjl/pr14370
hjl/pr14562/2.16
hjl/pr14562/master
hjl/pr14654
hjl/pr14716
hjl/pr14831
hjl/pr14937
hjl/pr14941
hjl/pr14955
hjl/pr14995
hjl/pr17711/2.18
hjl/pr17711/2.19
hjl/pr17711/2.20
hjl/pr17711/2.21
hjl/pr17841/2.21
hjl/pr17841/master
hjl/pr18078
hjl/pr18422
hjl/pr18661
hjl/pr18696
hjl/pr19122
hjl/pr19178/master
hjl/pr19363/2.22
hjl/pr19363/clobber
hjl/pr19363/master
hjl/pr19371/master
hjl/pr19463
hjl/pr19583
hjl/pr19590
hjl/pr19679/2.23
hjl/pr20309/master
hjl/pr21120/2.24
hjl/pr21120/2.25
hjl/pr21120/master
hjl/pr21258/2.23
hjl/pr21666/2.25
hjl/pr21666/master
hjl/pr21752/master
hjl/pr21815/master
hjl/pr21864/master
hjl/pr21913/master
hjl/pr21967/master
hjl/pr22053/master
hjl/pr22298/master
hjl/pr22353/master
hjl/pr22362/master
hjl/pr22363/master
hjl/pr23240/fw
hjl/pthread/2.21
hjl/pthread/2.22
hjl/release/2.20/master
hjl/size/master
hjl/tst-plt
hjl/unaligned
ibm/2.10/master
ibm/2.11/master
ibm/2.12/master
ibm/2.13/master
ibm/2.16/master
ibm/2.18/master
ibm/2.19/master
ibm/2.20/master
ibm/2.22/master
ibm/2.24/master
ibm/2.26/master
ibm/2.28/master
ibm/2.30/master
ibm/2.32/master
ibm/2.8/master
ibm/master
ldmitrie/intel_mpx
linaro/2.21/master
linaro/2.23/master
linaro/master
lxoliva/getaddrinfo
maskray/relr
maskray/stack_chk_guard
maskray/x86-mpx
master
mfabian/collation-update-2.27
neleai/string-x64
neleai/strlen
nsz/bti-1
nsz/btifix-v3
nsz/bug19329
nsz/bug19329-v2
nsz/bug23293
nsz/bug23293-v5
nsz/bug23293-v6
nsz/bug27072
nsz/math
nsz/mathvec
nsz/mtag
nsz/mtag-2
nsz/pacbti-v4
nsz/pacbti-v5
nsz/pacbti-v6
nsz/pacbti-v7
pasky/fixes
pasky/fixes-overdue
pranavk/grte_v5_plus
rearnsha/mte-v3.0
rearnsha/mte-v4.0
release/2.10/master
release/2.11/master
release/2.12/master
release/2.13/master
release/2.14/master
release/2.15/master
release/2.16/master
release/2.17/master
release/2.18/master
release/2.19/master
release/2.20/master
release/2.21/master
release/2.22/master
release/2.23/master
release/2.24/master
release/2.25/master
release/2.26/master
release/2.27/master
release/2.28/master
release/2.29/master
release/2.30/master
release/2.31/master
release/2.32/master
release/2.33/master
release/2.34/master
release/2.35/master
release/2.36/master
release/2.37/master
release/2.38/master
release/2.39/master
release/2.40/master
release/2.41/master
roland/Wshadow
roland/add-on-abi-tags
roland/backtrace-syms
roland/cancelhandling
roland/disable-nis
roland/getpid
roland/gold-vs-libc
roland/hwcap_mask
roland/manual-check
roland/nacl-debug-hack
roland/nacl-exit-stacks
roland/nacl-port/master
roland/nptl_db
roland/pthread_attr_getstack
roland/stat64
roland/sysconf-clocks
roland/tempname
roland/x86_64-crt1-cfi
rsa/2.17_backports
rsa/2.17_backports_v2
rsa/2.17_backports_v3
rsa/hwcap2_v3
rsa/hwcap2_v4
rsa/hwcap2_v5
rsa/hwcap2_v6
rsa/power8
rsa/power8_partial
rsa/stdint
rsa/stdint_headers
rsa/stdint_noheaders
rth/aa-memset
rth/aa-opt
rth/execl
rth/tramp
sasha/execveat
schwab/ilp32
shebs/clangify
siddhesh/changelog-begone
siddhesh/is_in_module
siddhesh/mmap-fallback
siddhesh/posix-wundef
siddhesh/realpath-and-getcwd
siddhesh/sem_timedwait
tuliom/float128
tuliom/libmvec
tuliom/microwatt
tuliom/multilib
users/skpgkp2/2.33/master
vineet/arc-glibc-2.30-time_t-32-bit
zack/anon-unions
zack/build-experiments
zack/build-layout-experiment
zack/elf-builtin-expect-conversion
zack/errno-prettyprint
zack/gtod-no-timezone
zack/no-nested-includes
zack/obsolete-time-functions
zack/remove-libcrypt
zack/wip-check-localplt-2
zack/wip-pthread-no-dupe-defns
origin/release/2.17/master
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stdio-common
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s="hl com"> F floating point state register.
p Processor state register.
N Branch predict clear ",pn" (v9)
T Branch predict set ",pt" (v9)
z %icc. (v9)
Z %xcc. (v9)
q Floating point queue.
r Single register that is both rs1 and rd.
O Single register that is both rs2 and rd.
Q Coprocessor queue.
S Special case.
t Trap base register.
w Window invalid mask register.
y Y register.
u sparclet coprocessor registers in rd position
U sparclet coprocessor registers in rs1 position
E %ccr. (v9)
s %fprs. (v9)
P %pc. (v9)
W %tick. (v9)
o %asi. (v9)
6 %fcc0. (v9)
7 %fcc1. (v9)
8 %fcc2. (v9)
9 %fcc3. (v9)
! Privileged Register in rd (v9)
? Privileged Register in rs1 (v9)
* Prefetch function constant. (v9)
x OPF field (v9 impdep).
0 32/64 bit immediate for set or setx (v9) insns
_ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a)
The following chars are unused: (note: ,[] are used as punctuation)
[45]
*/
#define OP2(x) (((x)&0x7) << 22)
/* op2 field of format2 insns */
#define OP3(x) (((x)&0x3f) << 19)
/* op3 field of format3 insns */
#define OP(x) ((unsigned)((x)&0x3) << 30)
/* op field of all insns */
#define OPF(x) (((x)&0x1ff) << 5)
/* opf field of float insns */
#define OPF_LOW5(x) OPF((x)&0x1f)
/* v9 */
#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z))
/* format3 float insns */
#define F3I(x) (((x)&0x1) << 13)
/* immediate field of format 3 insns */
#define F2(x, y) (OP(x) | OP2(y))
/* format 2 insns */
#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z))
/* format3 insns */
#define F1(x) (OP(x))
#define DISP30(x) ((x)&0x3fffffff)
#define ASI(x) (((x)&0xff) << 5)
/* asi field of format3 insns */
#define RS2(x) ((x)&0x1f)
/* rs2 field */
#define SIMM13(x) ((x)&0x1fff)
/* simm13 field */
#define RD(x) (((x)&0x1f) << 25)
/* destination register field */
#define RS1(x) (((x)&0x1f) << 14)
/* rs1 field */
#define ASI_RS2(x) (SIMM13(x))
#define MEMBAR(x) ((x)&0x7f)
#define SLCPOP(x) (((x)&0x7f) << 6)
/* sparclet cpop */
#define ANNUL (1<<29)
#define BPRED (1<<19)
/* v9 */
#define IMMED F3I(1)
#define RD_G0 RD(~0)
#define RS1_G0 RS1(~0)
#define RS2_G0 RS2(~0)
extern
const struct
sparc_opcode sparc_opcodes
[];
extern
const int
sparc_num_opcodes
;
extern
int
sparc_encode_asi
PARAMS
((
const char
*));
extern
const char
*
sparc_decode_asi
PARAMS
((
int
));
extern
int
sparc_encode_membar
PARAMS
((
const char
*));
extern
const char
*
sparc_decode_membar
PARAMS
((
int
));
extern
int
sparc_encode_prefetch
PARAMS
((
const char
*));
extern
const char
*
sparc_decode_prefetch
PARAMS
((
int
));
extern
int
sparc_encode_sparclet_cpreg
PARAMS
((
const char
*));
extern
const char
*
sparc_decode_sparclet_cpreg
PARAMS
((
int
));
/* Some defines to make life easy. */
#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
/* Bit masks of architectures supporting the insn. */
#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
/* v6 insns not supported on the sparclet */
#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
/* Although not all insns are implemented in hardware, sparclite is defined
to be a superset of v8. Unimplemented insns trap and are then theoretically
implemented in software.
It's not clear that the same is true for sparclet, although the docs
suggest it is. Rather than complicating things, the sparclet assembler
recognizes all v8 insns. */
#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
| MASK_V9 | MASK_V9A | MASK_V9B)
#define sparclet (MASK_SPARCLET)
#define sparclite (MASK_SPARCLITE)
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
#define v9a (MASK_V9A | MASK_V9B)
#define v9b (MASK_V9B)
/* v6 insns not supported by v9 */
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
| MASK_SPARCLET | MASK_SPARCLITE)
/* v9a instructions which would appear to be aliases to v9's impdep's
otherwise */
#define v9notv9a (MASK_V9)
/* Table of opcode architectures.
The order is defined in opcode/sparc.h. */
const struct
sparc_opcode_arch sparc_opcode_archs
[] = {
{
"v6"
,
MASK_V6
},
{
"v7"
,
MASK_V6
|
MASK_V7
},
{
"v8"
,
MASK_V6
|
MASK_V7
|
MASK_V8
},
{
"sparclet"
,
MASK_V6
|
MASK_V7
|
MASK_V8
|
MASK_SPARCLET
},
{
"sparclite"
,
MASK_V6
|
MASK_V7
|
MASK_V8
|
MASK_SPARCLITE
},
/* ??? Don't some v8 privileged insns conflict with v9? */
{
"v9"
,
MASK_V6
|
MASK_V7
|
MASK_V8
|
MASK_V9
},
/* v9 with ultrasparc additions */
{
"v9a"
,
MASK_V6
|
MASK_V7
|
MASK_V8
|
MASK_V9
|
MASK_V9A
},
/* v9 with cheetah additions */
{
"v9b"
,
MASK_V6
|
MASK_V7
|
MASK_V8
|
MASK_V9
|
MASK_V9A
|
MASK_V9B
},
{
NULL
,
0
}
};
/* Given NAME, return it's architecture entry. */
enum
sparc_opcode_arch_val
sparc_opcode_lookup_arch
(
name
)
const char
*
name
;
{
const struct
sparc_opcode_arch
*
p
;
for
(
p
= &
sparc_opcode_archs
[
0
];
p
->
name
; ++
p
)
{
if
(
strcmp
(
name
,
p
->
name
) ==
0
)
return
(
enum
sparc_opcode_arch_val
) (
p
- &
sparc_opcode_archs
[
0
]);
}
return
SPARC_OPCODE_ARCH_BAD
;
}
/* Branch condition field. */
#define COND(x) (((x)&0xf)<<25)
/* v9: Move (MOVcc and FMOVcc) condition field. */
#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14)))
/* v9 */
/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
#define RCOND(x) (((x)&0x7)<<10)
/* v9 */
#define CONDA (COND(0x8))
#define CONDCC (COND(0xd))
#define CONDCS (COND(0x5))
#define CONDE (COND(0x1))
#define CONDG (COND(0xa))
#define CONDGE (COND(0xb))
#define CONDGU (COND(0xc))
#define CONDL (COND(0x3))
#define CONDLE (COND(0x2))
#define CONDLEU (COND(0x4))
#define CONDN (COND(0x0))
#define CONDNE (COND(0x9))
#define CONDNEG (COND(0x6))
#define CONDPOS (COND(0xe))
#define CONDVC (COND(0xf))
#define CONDVS (COND(0x7))
#define CONDNZ CONDNE
#define CONDZ CONDE
#define CONDGEU CONDCC
#define CONDLU CONDCS
#define FCONDA (COND(0x8))
#define FCONDE (COND(0x9))
#define FCONDG (COND(0x6))
#define FCONDGE (COND(0xb))
#define FCONDL (COND(0x4))
#define FCONDLE (COND(0xd))
#define FCONDLG (COND(0x2))
#define FCONDN (COND(0x0))
#define FCONDNE (COND(0x1))
#define FCONDO (COND(0xf))
#define FCONDU (COND(0x7))
#define FCONDUE (COND(0xa))
#define FCONDUG (COND(0x5))
#define FCONDUGE (COND(0xc))
#define FCONDUL (COND(0x3))
#define FCONDULE (COND(0xe))
#define FCONDNZ FCONDNE
#define FCONDZ FCONDE
#define ICC (0)
/* v9 */
#define XCC (1<<12)
/* v9 */
#define FCC(x) (((x)&0x3)<<11)
/* v9 */
#define FBFCC(x) (((x)&0x3)<<20)
/* v9 */
/* The order of the opcodes in the table is significant:
* The assembler requires that all instances of the same mnemonic must
be consecutive. If they aren't, the assembler will bomb at runtime.
* The disassembler should not care about the order of the opcodes.
*/
/* Entries for commutative arithmetic operations. */
/* ??? More entries can make use of this. */
#define COMMUTEOP(opcode, op3, arch_mask) \
{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),
"1,2,d"
, 0, arch_mask }, \
{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1),
"1,i,d"
, 0, arch_mask }, \
{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1),
"i,1,d"
, 0, arch_mask }
const struct
sparc_opcode sparc_opcodes
[] = {
{
"ld"
,
F3
(
3
,
0x00
,
0
),
F3
(~
3
, ~
0x00
, ~
0
),
"[1+2],d"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x00
,
0
),
F3
(~
3
, ~
0x00
, ~
0
)|
RS2_G0
,
"[1],d"
,
0
,
v6
},
/* ld [rs1+%g0],d */
{
"ld"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
),
"[1+i],d"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
),
"[i+1],d"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v6
},
/* ld [rs1+0],d */
{
"ld"
,
F3
(
3
,
0x20
,
0
),
F3
(~
3
, ~
0x20
, ~
0
),
"[1+2],g"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x20
,
0
),
F3
(~
3
, ~
0x20
, ~
0
)|
RS2_G0
,
"[1],g"
,
0
,
v6
},
/* ld [rs1+%g0],d */
{
"ld"
,
F3
(
3
,
0x20
,
1
),
F3
(~
3
, ~
0x20
, ~
1
),
"[1+i],g"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x20
,
1
),
F3
(~
3
, ~
0x20
, ~
1
),
"[i+1],g"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x20
,
1
),
F3
(~
3
, ~
0x20
, ~
1
)|
RS1_G0
,
"[i],g"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x20
,
1
),
F3
(~
3
, ~
0x20
, ~
1
)|
SIMM13
(~
0
),
"[1],g"
,
0
,
v6
},
/* ld [rs1+0],d */
{
"ld"
,
F3
(
3
,
0x21
,
0
),
F3
(~
3
, ~
0x21
, ~
0
)|
RD
(~
0
),
"[1+2],F"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x21
,
0
),
F3
(~
3
, ~
0x21
, ~
0
)|
RS2_G0
|
RD
(~
0
),
"[1],F"
,
0
,
v6
},
/* ld [rs1+%g0],d */
{
"ld"
,
F3
(
3
,
0x21
,
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
RD
(~
0
),
"[1+i],F"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x21
,
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
RD
(~
0
),
"[i+1],F"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x21
,
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
RS1_G0
|
RD
(~
0
),
"[i],F"
,
0
,
v6
},
{
"ld"
,
F3
(
3
,
0x21
,
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
SIMM13
(~
0
)|
RD
(~
0
),
"[1],F"
,
0
,
v6
},
/* ld [rs1+0],d */
{
"ld"
,
F3
(
3
,
0x30
,
0
),
F3
(~
3
, ~
0x30
, ~
0
),
"[1+2],D"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x30
,
0
),
F3
(~
3
, ~
0x30
, ~
0
)|
RS2_G0
,
"[1],D"
,
0
,
v6notv9
},
/* ld [rs1+%g0],d */
{
"ld"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
),
"[1+i],D"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
),
"[i+1],D"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
)|
RS1_G0
,
"[i],D"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
)|
SIMM13
(~
0
),
"[1],D"
,
0
,
v6notv9
},
/* ld [rs1+0],d */
{
"ld"
,
F3
(
3
,
0x31
,
0
),
F3
(~
3
, ~
0x31
, ~
0
),
"[1+2],C"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x31
,
0
),
F3
(~
3
, ~
0x31
, ~
0
)|
RS2_G0
,
"[1],C"
,
0
,
v6notv9
},
/* ld [rs1+%g0],d */
{
"ld"
,
F3
(
3
,
0x31
,
1
),
F3
(~
3
, ~
0x31
, ~
1
),
"[1+i],C"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x31
,
1
),
F3
(~
3
, ~
0x31
, ~
1
),
"[i+1],C"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x31
,
1
),
F3
(~
3
, ~
0x31
, ~
1
)|
RS1_G0
,
"[i],C"
,
0
,
v6notv9
},
{
"ld"
,
F3
(
3
,
0x31
,
1
),
F3
(~
3
, ~
0x31
, ~
1
)|
SIMM13
(~
0
),
"[1],C"
,
0
,
v6notv9
},
/* ld [rs1+0],d */
/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
'ld' pseudo-op in v9. */
{
"lduw"
,
F3
(
3
,
0x00
,
0
),
F3
(~
3
, ~
0x00
, ~
0
),
"[1+2],d"
,
F_ALIAS
,
v9
},
{
"lduw"
,
F3
(
3
,
0x00
,
0
),
F3
(~
3
, ~
0x00
, ~
0
)|
RS2_G0
,
"[1],d"
,
F_ALIAS
,
v9
},
/* ld [rs1+%g0],d */
{
"lduw"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
),
"[1+i],d"
,
F_ALIAS
,
v9
},
{
"lduw"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
),
"[i+1],d"
,
F_ALIAS
,
v9
},
{
"lduw"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
)|
RS1_G0
,
"[i],d"
,
F_ALIAS
,
v9
},
{
"lduw"
,
F3
(
3
,
0x00
,
1
),
F3
(~
3
, ~
0x00
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
F_ALIAS
,
v9
},
/* ld [rs1+0],d */
{
"ldd"
,
F3
(
3
,
0x03
,
0
),
F3
(~
3
, ~
0x03
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x03
,
0
),
F3
(~
3
, ~
0x03
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldd [rs1+%g0],d */
{
"ldd"
,
F3
(
3
,
0x03
,
1
),
F3
(~
3
, ~
0x03
, ~
1
),
"[1+i],d"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x03
,
1
),
F3
(~
3
, ~
0x03
, ~
1
),
"[i+1],d"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x03
,
1
),
F3
(~
3
, ~
0x03
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x03
,
1
),
F3
(~
3
, ~
0x03
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldd [rs1+0],d */
{
"ldd"
,
F3
(
3
,
0x23
,
0
),
F3
(~
3
, ~
0x23
, ~
0
)|
ASI
(~
0
),
"[1+2],H"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x23
,
0
),
F3
(~
3
, ~
0x23
, ~
0
)|
ASI_RS2
(~
0
),
"[1],H"
,
0
,
v6
},
/* ldd [rs1+%g0],d */
{
"ldd"
,
F3
(
3
,
0x23
,
1
),
F3
(~
3
, ~
0x23
, ~
1
),
"[1+i],H"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x23
,
1
),
F3
(~
3
, ~
0x23
, ~
1
),
"[i+1],H"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x23
,
1
),
F3
(~
3
, ~
0x23
, ~
1
)|
RS1_G0
,
"[i],H"
,
0
,
v6
},
{
"ldd"
,
F3
(
3
,
0x23
,
1
),
F3
(~
3
, ~
0x23
, ~
1
)|
SIMM13
(~
0
),
"[1],H"
,
0
,
v6
},
/* ldd [rs1+0],d */
{
"ldd"
,
F3
(
3
,
0x33
,
0
),
F3
(~
3
, ~
0x33
, ~
0
)|
ASI
(~
0
),
"[1+2],D"
,
0
,
v6notv9
},
{
"ldd"
,
F3
(
3
,
0x33
,
0
),
F3
(~
3
, ~
0x33
, ~
0
)|
ASI_RS2
(~
0
),
"[1],D"
,
0
,
v6notv9
},
/* ldd [rs1+%g0],d */
{
"ldd"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
),
"[1+i],D"
,
0
,
v6notv9
},
{
"ldd"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
),
"[i+1],D"
,
0
,
v6notv9
},
{
"ldd"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
)|
RS1_G0
,
"[i],D"
,
0
,
v6notv9
},
{
"ldd"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
)|
SIMM13
(~
0
),
"[1],D"
,
0
,
v6notv9
},
/* ldd [rs1+0],d */
{
"ldq"
,
F3
(
3
,
0x22
,
0
),
F3
(~
3
, ~
0x22
, ~
0
)|
ASI
(~
0
),
"[1+2],J"
,
0
,
v9
},
{
"ldq"
,
F3
(
3
,
0x22
,
0
),
F3
(~
3
, ~
0x22
, ~
0
)|
ASI_RS2
(~
0
),
"[1],J"
,
0
,
v9
},
/* ldd [rs1+%g0],d */
{
"ldq"
,
F3
(
3
,
0x22
,
1
),
F3
(~
3
, ~
0x22
, ~
1
),
"[1+i],J"
,
0
,
v9
},
{
"ldq"
,
F3
(
3
,
0x22
,
1
),
F3
(~
3
, ~
0x22
, ~
1
),
"[i+1],J"
,
0
,
v9
},
{
"ldq"
,
F3
(
3
,
0x22
,
1
),
F3
(~
3
, ~
0x22
, ~
1
)|
RS1_G0
,
"[i],J"
,
0
,
v9
},
{
"ldq"
,
F3
(
3
,
0x22
,
1
),
F3
(~
3
, ~
0x22
, ~
1
)|
SIMM13
(~
0
),
"[1],J"
,
0
,
v9
},
/* ldd [rs1+0],d */
{
"ldsb"
,
F3
(
3
,
0x09
,
0
),
F3
(~
3
, ~
0x09
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v6
},
{
"ldsb"
,
F3
(
3
,
0x09
,
0
),
F3
(~
3
, ~
0x09
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldsb [rs1+%g0],d */
{
"ldsb"
,
F3
(
3
,
0x09
,
1
),
F3
(~
3
, ~
0x09
, ~
1
),
"[1+i],d"
,
0
,
v6
},
{
"ldsb"
,
F3
(
3
,
0x09
,
1
),
F3
(~
3
, ~
0x09
, ~
1
),
"[i+1],d"
,
0
,
v6
},
{
"ldsb"
,
F3
(
3
,
0x09
,
1
),
F3
(~
3
, ~
0x09
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v6
},
{
"ldsb"
,
F3
(
3
,
0x09
,
1
),
F3
(~
3
, ~
0x09
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldsb [rs1+0],d */
{
"ldsh"
,
F3
(
3
,
0x0a
,
0
),
F3
(~
3
, ~
0x0a
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldsh [rs1+%g0],d */
{
"ldsh"
,
F3
(
3
,
0x0a
,
0
),
F3
(~
3
, ~
0x0a
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v6
},
{
"ldsh"
,
F3
(
3
,
0x0a
,
1
),
F3
(~
3
, ~
0x0a
, ~
1
),
"[1+i],d"
,
0
,
v6
},
{
"ldsh"
,
F3
(
3
,
0x0a
,
1
),
F3
(~
3
, ~
0x0a
, ~
1
),
"[i+1],d"
,
0
,
v6
},
{
"ldsh"
,
F3
(
3
,
0x0a
,
1
),
F3
(~
3
, ~
0x0a
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v6
},
{
"ldsh"
,
F3
(
3
,
0x0a
,
1
),
F3
(~
3
, ~
0x0a
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldsh [rs1+0],d */
{
"ldstub"
,
F3
(
3
,
0x0d
,
0
),
F3
(~
3
, ~
0x0d
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v6
},
{
"ldstub"
,
F3
(
3
,
0x0d
,
0
),
F3
(~
3
, ~
0x0d
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldstub [rs1+%g0],d */
{
"ldstub"
,
F3
(
3
,
0x0d
,
1
),
F3
(~
3
, ~
0x0d
, ~
1
),
"[1+i],d"
,
0
,
v6
},
{
"ldstub"
,
F3
(
3
,
0x0d
,
1
),
F3
(~
3
, ~
0x0d
, ~
1
),
"[i+1],d"
,
0
,
v6
},
{
"ldstub"
,
F3
(
3
,
0x0d
,
1
),
F3
(~
3
, ~
0x0d
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v6
},
{
"ldstub"
,
F3
(
3
,
0x0d
,
1
),
F3
(~
3
, ~
0x0d
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldstub [rs1+0],d */
{
"ldsw"
,
F3
(
3
,
0x08
,
0
),
F3
(~
3
, ~
0x08
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v9
},
{
"ldsw"
,
F3
(
3
,
0x08
,
0
),
F3
(~
3
, ~
0x08
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v9
},
/* ldsw [rs1+%g0],d */
{
"ldsw"
,
F3
(
3
,
0x08
,
1
),
F3
(~
3
, ~
0x08
, ~
1
),
"[1+i],d"
,
0
,
v9
},
{
"ldsw"
,
F3
(
3
,
0x08
,
1
),
F3
(~
3
, ~
0x08
, ~
1
),
"[i+1],d"
,
0
,
v9
},
{
"ldsw"
,
F3
(
3
,
0x08
,
1
),
F3
(~
3
, ~
0x08
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v9
},
{
"ldsw"
,
F3
(
3
,
0x08
,
1
),
F3
(~
3
, ~
0x08
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v9
},
/* ldsw [rs1+0],d */
{
"ldub"
,
F3
(
3
,
0x01
,
0
),
F3
(~
3
, ~
0x01
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v6
},
{
"ldub"
,
F3
(
3
,
0x01
,
0
),
F3
(~
3
, ~
0x01
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldub [rs1+%g0],d */
{
"ldub"
,
F3
(
3
,
0x01
,
1
),
F3
(~
3
, ~
0x01
, ~
1
),
"[1+i],d"
,
0
,
v6
},
{
"ldub"
,
F3
(
3
,
0x01
,
1
),
F3
(~
3
, ~
0x01
, ~
1
),
"[i+1],d"
,
0
,
v6
},
{
"ldub"
,
F3
(
3
,
0x01
,
1
),
F3
(~
3
, ~
0x01
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v6
},
{
"ldub"
,
F3
(
3
,
0x01
,
1
),
F3
(~
3
, ~
0x01
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v6
},
/* ldub [rs1+0],d */
{
"lduh"
,
F3
(
3
,
0x02
,
0
),
F3
(~
3
, ~
0x02
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v6
},
{
"lduh"
,
F3
(
3
,
0x02
,
0
),
F3
(~
3
, ~
0x02
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v6
},
/* lduh [rs1+%g0],d */
{
"lduh"
,
F3
(
3
,
0x02
,
1
),
F3
(~
3
, ~
0x02
, ~
1
),
"[1+i],d"
,
0
,
v6
},
{
"lduh"
,
F3
(
3
,
0x02
,
1
),
F3
(~
3
, ~
0x02
, ~
1
),
"[i+1],d"
,
0
,
v6
},
{
"lduh"
,
F3
(
3
,
0x02
,
1
),
F3
(~
3
, ~
0x02
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v6
},
{
"lduh"
,
F3
(
3
,
0x02
,
1
),
F3
(~
3
, ~
0x02
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v6
},
/* lduh [rs1+0],d */
{
"ldx"
,
F3
(
3
,
0x0b
,
0
),
F3
(~
3
, ~
0x0b
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x0b
,
0
),
F3
(~
3
, ~
0x0b
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v9
},
/* ldx [rs1+%g0],d */
{
"ldx"
,
F3
(
3
,
0x0b
,
1
),
F3
(~
3
, ~
0x0b
, ~
1
),
"[1+i],d"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x0b
,
1
),
F3
(~
3
, ~
0x0b
, ~
1
),
"[i+1],d"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x0b
,
1
),
F3
(~
3
, ~
0x0b
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x0b
,
1
),
F3
(~
3
, ~
0x0b
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v9
},
/* ldx [rs1+0],d */
{
"ldx"
,
F3
(
3
,
0x21
,
0
)|
RD
(
1
),
F3
(~
3
, ~
0x21
, ~
0
)|
RD
(~
1
),
"[1+2],F"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x21
,
0
)|
RD
(
1
),
F3
(~
3
, ~
0x21
, ~
0
)|
RS2_G0
|
RD
(~
1
),
"[1],F"
,
0
,
v9
},
/* ld [rs1+%g0],d */
{
"ldx"
,
F3
(
3
,
0x21
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
RD
(~
1
),
"[1+i],F"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x21
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
RD
(~
1
),
"[i+1],F"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x21
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
RS1_G0
|
RD
(~
1
),
"[i],F"
,
0
,
v9
},
{
"ldx"
,
F3
(
3
,
0x21
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x21
, ~
1
)|
SIMM13
(~
0
)|
RD
(~
1
),
"[1],F"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"lda"
,
F3
(
3
,
0x10
,
0
),
F3
(~
3
, ~
0x10
, ~
0
),
"[1+2]A,d"
,
0
,
v6
},
{
"lda"
,
F3
(
3
,
0x10
,
0
),
F3
(~
3
, ~
0x10
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v6
},
/* lda [rs1+%g0],d */
{
"lda"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"lda"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"lda"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"lda"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"lda"
,
F3
(
3
,
0x30
,
0
),
F3
(~
3
, ~
0x30
, ~
0
),
"[1+2]A,g"
,
0
,
v9
},
{
"lda"
,
F3
(
3
,
0x30
,
0
),
F3
(~
3
, ~
0x30
, ~
0
)|
RS2_G0
,
"[1]A,g"
,
0
,
v9
},
/* lda [rs1+%g0],d */
{
"lda"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
),
"[1+i]o,g"
,
0
,
v9
},
{
"lda"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
),
"[i+1]o,g"
,
0
,
v9
},
{
"lda"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
)|
RS1_G0
,
"[i]o,g"
,
0
,
v9
},
{
"lda"
,
F3
(
3
,
0x30
,
1
),
F3
(~
3
, ~
0x30
, ~
1
)|
SIMM13
(~
0
),
"[1]o,g"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"ldda"
,
F3
(
3
,
0x13
,
0
),
F3
(~
3
, ~
0x13
, ~
0
),
"[1+2]A,d"
,
0
,
v6
},
{
"ldda"
,
F3
(
3
,
0x13
,
0
),
F3
(~
3
, ~
0x13
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v6
},
/* ldda [rs1+%g0],d */
{
"ldda"
,
F3
(
3
,
0x13
,
1
),
F3
(~
3
, ~
0x13
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"ldda"
,
F3
(
3
,
0x13
,
1
),
F3
(~
3
, ~
0x13
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"ldda"
,
F3
(
3
,
0x13
,
1
),
F3
(~
3
, ~
0x13
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"ldda"
,
F3
(
3
,
0x13
,
1
),
F3
(~
3
, ~
0x13
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"ldda"
,
F3
(
3
,
0x33
,
0
),
F3
(~
3
, ~
0x33
, ~
0
),
"[1+2]A,H"
,
0
,
v9
},
{
"ldda"
,
F3
(
3
,
0x33
,
0
),
F3
(~
3
, ~
0x33
, ~
0
)|
RS2_G0
,
"[1]A,H"
,
0
,
v9
},
/* ldda [rs1+%g0],d */
{
"ldda"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
),
"[1+i]o,H"
,
0
,
v9
},
{
"ldda"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
),
"[i+1]o,H"
,
0
,
v9
},
{
"ldda"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
)|
RS1_G0
,
"[i]o,H"
,
0
,
v9
},
{
"ldda"
,
F3
(
3
,
0x33
,
1
),
F3
(~
3
, ~
0x33
, ~
1
)|
SIMM13
(~
0
),
"[1]o,H"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"ldqa"
,
F3
(
3
,
0x32
,
0
),
F3
(~
3
, ~
0x32
, ~
0
),
"[1+2]A,J"
,
0
,
v9
},
{
"ldqa"
,
F3
(
3
,
0x32
,
0
),
F3
(~
3
, ~
0x32
, ~
0
)|
RS2_G0
,
"[1]A,J"
,
0
,
v9
},
/* ldd [rs1+%g0],d */
{
"ldqa"
,
F3
(
3
,
0x32
,
1
),
F3
(~
3
, ~
0x32
, ~
1
),
"[1+i]o,J"
,
0
,
v9
},
{
"ldqa"
,
F3
(
3
,
0x32
,
1
),
F3
(~
3
, ~
0x32
, ~
1
),
"[i+1]o,J"
,
0
,
v9
},
{
"ldqa"
,
F3
(
3
,
0x32
,
1
),
F3
(~
3
, ~
0x32
, ~
1
)|
RS1_G0
,
"[i]o,J"
,
0
,
v9
},
{
"ldqa"
,
F3
(
3
,
0x32
,
1
),
F3
(~
3
, ~
0x32
, ~
1
)|
SIMM13
(~
0
),
"[1]o,J"
,
0
,
v9
},
/* ldd [rs1+0],d */
{
"ldsba"
,
F3
(
3
,
0x19
,
0
),
F3
(~
3
, ~
0x19
, ~
0
),
"[1+2]A,d"
,
0
,
v6
},
{
"ldsba"
,
F3
(
3
,
0x19
,
0
),
F3
(~
3
, ~
0x19
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v6
},
/* ldsba [rs1+%g0],d */
{
"ldsba"
,
F3
(
3
,
0x19
,
1
),
F3
(~
3
, ~
0x19
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"ldsba"
,
F3
(
3
,
0x19
,
1
),
F3
(~
3
, ~
0x19
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"ldsba"
,
F3
(
3
,
0x19
,
1
),
F3
(~
3
, ~
0x19
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"ldsba"
,
F3
(
3
,
0x19
,
1
),
F3
(~
3
, ~
0x19
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"ldsha"
,
F3
(
3
,
0x1a
,
0
),
F3
(~
3
, ~
0x1a
, ~
0
),
"[1+2]A,d"
,
0
,
v6
},
{
"ldsha"
,
F3
(
3
,
0x1a
,
0
),
F3
(~
3
, ~
0x1a
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v6
},
/* ldsha [rs1+%g0],d */
{
"ldsha"
,
F3
(
3
,
0x1a
,
1
),
F3
(~
3
, ~
0x1a
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"ldsha"
,
F3
(
3
,
0x1a
,
1
),
F3
(~
3
, ~
0x1a
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"ldsha"
,
F3
(
3
,
0x1a
,
1
),
F3
(~
3
, ~
0x1a
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"ldsha"
,
F3
(
3
,
0x1a
,
1
),
F3
(~
3
, ~
0x1a
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"ldstuba"
,
F3
(
3
,
0x1d
,
0
),
F3
(~
3
, ~
0x1d
, ~
0
),
"[1+2]A,d"
,
0
,
v6
},
{
"ldstuba"
,
F3
(
3
,
0x1d
,
0
),
F3
(~
3
, ~
0x1d
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v6
},
/* ldstuba [rs1+%g0],d */
{
"ldstuba"
,
F3
(
3
,
0x1d
,
1
),
F3
(~
3
, ~
0x1d
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"ldstuba"
,
F3
(
3
,
0x1d
,
1
),
F3
(~
3
, ~
0x1d
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"ldstuba"
,
F3
(
3
,
0x1d
,
1
),
F3
(~
3
, ~
0x1d
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"ldstuba"
,
F3
(
3
,
0x1d
,
1
),
F3
(~
3
, ~
0x1d
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"ldswa"
,
F3
(
3
,
0x18
,
0
),
F3
(~
3
, ~
0x18
, ~
0
),
"[1+2]A,d"
,
0
,
v9
},
{
"ldswa"
,
F3
(
3
,
0x18
,
0
),
F3
(~
3
, ~
0x18
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v9
},
/* lda [rs1+%g0],d */
{
"ldswa"
,
F3
(
3
,
0x18
,
1
),
F3
(~
3
, ~
0x18
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"ldswa"
,
F3
(
3
,
0x18
,
1
),
F3
(~
3
, ~
0x18
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"ldswa"
,
F3
(
3
,
0x18
,
1
),
F3
(~
3
, ~
0x18
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"ldswa"
,
F3
(
3
,
0x18
,
1
),
F3
(~
3
, ~
0x18
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"lduba"
,
F3
(
3
,
0x11
,
0
),
F3
(~
3
, ~
0x11
, ~
0
),
"[1+2]A,d"
,
0
,
v6
},
{
"lduba"
,
F3
(
3
,
0x11
,
0
),
F3
(~
3
, ~
0x11
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v6
},
/* lduba [rs1+%g0],d */
{
"lduba"
,
F3
(
3
,
0x11
,
1
),
F3
(~
3
, ~
0x11
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"lduba"
,
F3
(
3
,
0x11
,
1
),
F3
(~
3
, ~
0x11
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"lduba"
,
F3
(
3
,
0x11
,
1
),
F3
(~
3
, ~
0x11
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"lduba"
,
F3
(
3
,
0x11
,
1
),
F3
(~
3
, ~
0x11
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"lduha"
,
F3
(
3
,
0x12
,
0
),
F3
(~
3
, ~
0x12
, ~
0
),
"[1+2]A,d"
,
0
,
v6
},
{
"lduha"
,
F3
(
3
,
0x12
,
0
),
F3
(~
3
, ~
0x12
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v6
},
/* lduha [rs1+%g0],d */
{
"lduha"
,
F3
(
3
,
0x12
,
1
),
F3
(~
3
, ~
0x12
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"lduha"
,
F3
(
3
,
0x12
,
1
),
F3
(~
3
, ~
0x12
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"lduha"
,
F3
(
3
,
0x12
,
1
),
F3
(~
3
, ~
0x12
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"lduha"
,
F3
(
3
,
0x12
,
1
),
F3
(~
3
, ~
0x12
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"lduwa"
,
F3
(
3
,
0x10
,
0
),
F3
(~
3
, ~
0x10
, ~
0
),
"[1+2]A,d"
,
F_ALIAS
,
v9
},
/* lduwa === lda */
{
"lduwa"
,
F3
(
3
,
0x10
,
0
),
F3
(~
3
, ~
0x10
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
F_ALIAS
,
v9
},
/* lda [rs1+%g0],d */
{
"lduwa"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
),
"[1+i]o,d"
,
F_ALIAS
,
v9
},
{
"lduwa"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
),
"[i+1]o,d"
,
F_ALIAS
,
v9
},
{
"lduwa"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
F_ALIAS
,
v9
},
{
"lduwa"
,
F3
(
3
,
0x10
,
1
),
F3
(~
3
, ~
0x10
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
F_ALIAS
,
v9
},
/* ld [rs1+0],d */
{
"ldxa"
,
F3
(
3
,
0x1b
,
0
),
F3
(~
3
, ~
0x1b
, ~
0
),
"[1+2]A,d"
,
0
,
v9
},
{
"ldxa"
,
F3
(
3
,
0x1b
,
0
),
F3
(~
3
, ~
0x1b
, ~
0
)|
RS2_G0
,
"[1]A,d"
,
0
,
v9
},
/* lda [rs1+%g0],d */
{
"ldxa"
,
F3
(
3
,
0x1b
,
1
),
F3
(~
3
, ~
0x1b
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"ldxa"
,
F3
(
3
,
0x1b
,
1
),
F3
(~
3
, ~
0x1b
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"ldxa"
,
F3
(
3
,
0x1b
,
1
),
F3
(~
3
, ~
0x1b
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"ldxa"
,
F3
(
3
,
0x1b
,
1
),
F3
(~
3
, ~
0x1b
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* ld [rs1+0],d */
{
"st"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
0
,
v6
},
/* st d,[rs1+%g0] */
{
"st"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[1+i]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[i+1]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RS1_G0
,
"d,[i]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
0
,
v6
},
/* st d,[rs1+0] */
{
"st"
,
F3
(
3
,
0x24
,
0
),
F3
(~
3
, ~
0x24
, ~
0
)|
ASI
(~
0
),
"g,[1+2]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x24
,
0
),
F3
(~
3
, ~
0x24
, ~
0
)|
ASI_RS2
(~
0
),
"g,[1]"
,
0
,
v6
},
/* st d[rs1+%g0] */
{
"st"
,
F3
(
3
,
0x24
,
1
),
F3
(~
3
, ~
0x24
, ~
1
),
"g,[1+i]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x24
,
1
),
F3
(~
3
, ~
0x24
, ~
1
),
"g,[i+1]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x24
,
1
),
F3
(~
3
, ~
0x24
, ~
1
)|
RS1_G0
,
"g,[i]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x24
,
1
),
F3
(~
3
, ~
0x24
, ~
1
)|
SIMM13
(~
0
),
"g,[1]"
,
0
,
v6
},
/* st d,[rs1+0] */
{
"st"
,
F3
(
3
,
0x34
,
0
),
F3
(~
3
, ~
0x34
, ~
0
)|
ASI
(~
0
),
"D,[1+2]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x34
,
0
),
F3
(~
3
, ~
0x34
, ~
0
)|
ASI_RS2
(~
0
),
"D,[1]"
,
0
,
v6notv9
},
/* st d,[rs1+%g0] */
{
"st"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
),
"D,[1+i]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
),
"D,[i+1]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
)|
RS1_G0
,
"D,[i]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
)|
SIMM13
(~
0
),
"D,[1]"
,
0
,
v6notv9
},
/* st d,[rs1+0] */
{
"st"
,
F3
(
3
,
0x35
,
0
),
F3
(~
3
, ~
0x35
, ~
0
)|
ASI
(~
0
),
"C,[1+2]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x35
,
0
),
F3
(~
3
, ~
0x35
, ~
0
)|
ASI_RS2
(~
0
),
"C,[1]"
,
0
,
v6notv9
},
/* st d,[rs1+%g0] */
{
"st"
,
F3
(
3
,
0x35
,
1
),
F3
(~
3
, ~
0x35
, ~
1
),
"C,[1+i]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x35
,
1
),
F3
(~
3
, ~
0x35
, ~
1
),
"C,[i+1]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x35
,
1
),
F3
(~
3
, ~
0x35
, ~
1
)|
RS1_G0
,
"C,[i]"
,
0
,
v6notv9
},
{
"st"
,
F3
(
3
,
0x35
,
1
),
F3
(~
3
, ~
0x35
, ~
1
)|
SIMM13
(~
0
),
"C,[1]"
,
0
,
v6notv9
},
/* st d,[rs1+0] */
{
"st"
,
F3
(
3
,
0x25
,
0
),
F3
(~
3
, ~
0x25
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"F,[1+2]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x25
,
0
),
F3
(~
3
, ~
0x25
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"F,[1]"
,
0
,
v6
},
/* st d,[rs1+%g0] */
{
"st"
,
F3
(
3
,
0x25
,
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
RD_G0
,
"F,[1+i]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x25
,
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
RD_G0
,
"F,[i+1]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x25
,
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
RD_G0
|
RS1_G0
,
"F,[i]"
,
0
,
v6
},
{
"st"
,
F3
(
3
,
0x25
,
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
RD_G0
|
SIMM13
(~
0
),
"F,[1]"
,
0
,
v6
},
/* st d,[rs1+0] */
{
"stw"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v9
},
{
"stw"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v9
},
/* st d,[rs1+%g0] */
{
"stw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v9
},
{
"stw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v9
},
{
"stw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v9
},
{
"stw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v9
},
/* st d,[rs1+0] */
{
"stsw"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v9
},
{
"stsw"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v9
},
/* st d,[rs1+%g0] */
{
"stsw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v9
},
{
"stsw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v9
},
{
"stsw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v9
},
{
"stsw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v9
},
/* st d,[rs1+0] */
{
"stuw"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v9
},
{
"stuw"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v9
},
/* st d,[rs1+%g0] */
{
"stuw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v9
},
{
"stuw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v9
},
{
"stuw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v9
},
{
"stuw"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v9
},
/* st d,[rs1+0] */
{
"spill"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v6
},
{
"spill"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* st d,[rs1+%g0] */
{
"spill"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v6
},
{
"spill"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v6
},
{
"spill"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v6
},
{
"spill"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* st d,[rs1+0] */
{
"sta"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
),
"d,[1+2]A"
,
0
,
v6
},
{
"sta"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
0
,
v6
},
/* sta d,[rs1+%g0] */
{
"sta"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[1+i]o"
,
0
,
v9
},
{
"sta"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[i+1]o"
,
0
,
v9
},
{
"sta"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
0
,
v9
},
{
"sta"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
0
,
v9
},
/* st d,[rs1+0] */
{
"sta"
,
F3
(
3
,
0x34
,
0
),
F3
(~
3
, ~
0x34
, ~
0
),
"g,[1+2]A"
,
0
,
v9
},
{
"sta"
,
F3
(
3
,
0x34
,
0
),
F3
(~
3
, ~
0x34
, ~
0
)|
RS2
(~
0
),
"g,[1]A"
,
0
,
v9
},
/* sta d,[rs1+%g0] */
{
"sta"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
),
"g,[1+i]o"
,
0
,
v9
},
{
"sta"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
),
"g,[i+1]o"
,
0
,
v9
},
{
"sta"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
)|
RS1_G0
,
"g,[i]o"
,
0
,
v9
},
{
"sta"
,
F3
(
3
,
0x34
,
1
),
F3
(~
3
, ~
0x34
, ~
1
)|
SIMM13
(~
0
),
"g,[1]o"
,
0
,
v9
},
/* st d,[rs1+0] */
{
"stwa"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
),
"d,[1+2]A"
,
F_ALIAS
,
v9
},
{
"stwa"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
F_ALIAS
,
v9
},
/* sta d,[rs1+%g0] */
{
"stwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[1+i]o"
,
F_ALIAS
,
v9
},
{
"stwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[i+1]o"
,
F_ALIAS
,
v9
},
{
"stwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
F_ALIAS
,
v9
},
{
"stwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
F_ALIAS
,
v9
},
/* st d,[rs1+0] */
{
"stswa"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
),
"d,[1+2]A"
,
F_ALIAS
,
v9
},
{
"stswa"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
F_ALIAS
,
v9
},
/* sta d,[rs1+%g0] */
{
"stswa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[1+i]o"
,
F_ALIAS
,
v9
},
{
"stswa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[i+1]o"
,
F_ALIAS
,
v9
},
{
"stswa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
F_ALIAS
,
v9
},
{
"stswa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
F_ALIAS
,
v9
},
/* st d,[rs1+0] */
{
"stuwa"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
),
"d,[1+2]A"
,
F_ALIAS
,
v9
},
{
"stuwa"
,
F3
(
3
,
0x14
,
0
),
F3
(~
3
, ~
0x14
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
F_ALIAS
,
v9
},
/* sta d,[rs1+%g0] */
{
"stuwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[1+i]o"
,
F_ALIAS
,
v9
},
{
"stuwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
),
"d,[i+1]o"
,
F_ALIAS
,
v9
},
{
"stuwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
F_ALIAS
,
v9
},
{
"stuwa"
,
F3
(
3
,
0x14
,
1
),
F3
(~
3
, ~
0x14
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
F_ALIAS
,
v9
},
/* st d,[rs1+0] */
{
"stb"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
0
,
v6
},
{
"stb"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
0
,
v6
},
/* stb d,[rs1+%g0] */
{
"stb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
),
"d,[1+i]"
,
0
,
v6
},
{
"stb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
),
"d,[i+1]"
,
0
,
v6
},
{
"stb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
RS1_G0
,
"d,[i]"
,
0
,
v6
},
{
"stb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
0
,
v6
},
/* stb d,[rs1+0] */
{
"stsb"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v6
},
{
"stsb"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* stb d,[rs1+%g0] */
{
"stsb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v6
},
{
"stsb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v6
},
{
"stsb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v6
},
{
"stsb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* stb d,[rs1+0] */
{
"stub"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v6
},
{
"stub"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* stb d,[rs1+%g0] */
{
"stub"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v6
},
{
"stub"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v6
},
{
"stub"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v6
},
{
"stub"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* stb d,[rs1+0] */
{
"stba"
,
F3
(
3
,
0x15
,
0
),
F3
(~
3
, ~
0x15
, ~
0
),
"d,[1+2]A"
,
0
,
v6
},
{
"stba"
,
F3
(
3
,
0x15
,
0
),
F3
(~
3
, ~
0x15
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
0
,
v6
},
/* stba d,[rs1+%g0] */
{
"stba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
),
"d,[1+i]o"
,
0
,
v9
},
{
"stba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
),
"d,[i+1]o"
,
0
,
v9
},
{
"stba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
0
,
v9
},
{
"stba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
0
,
v9
},
/* stb d,[rs1+0] */
{
"stsba"
,
F3
(
3
,
0x15
,
0
),
F3
(~
3
, ~
0x15
, ~
0
),
"d,[1+2]A"
,
F_ALIAS
,
v6
},
{
"stsba"
,
F3
(
3
,
0x15
,
0
),
F3
(~
3
, ~
0x15
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
F_ALIAS
,
v6
},
/* stba d,[rs1+%g0] */
{
"stsba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
),
"d,[1+i]o"
,
F_ALIAS
,
v9
},
{
"stsba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
),
"d,[i+1]o"
,
F_ALIAS
,
v9
},
{
"stsba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
F_ALIAS
,
v9
},
{
"stsba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
F_ALIAS
,
v9
},
/* stb d,[rs1+0] */
{
"stuba"
,
F3
(
3
,
0x15
,
0
),
F3
(~
3
, ~
0x15
, ~
0
),
"d,[1+2]A"
,
F_ALIAS
,
v6
},
{
"stuba"
,
F3
(
3
,
0x15
,
0
),
F3
(~
3
, ~
0x15
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
F_ALIAS
,
v6
},
/* stba d,[rs1+%g0] */
{
"stuba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
),
"d,[1+i]o"
,
F_ALIAS
,
v9
},
{
"stuba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
),
"d,[i+1]o"
,
F_ALIAS
,
v9
},
{
"stuba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
F_ALIAS
,
v9
},
{
"stuba"
,
F3
(
3
,
0x15
,
1
),
F3
(~
3
, ~
0x15
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
F_ALIAS
,
v9
},
/* stb d,[rs1+0] */
{
"std"
,
F3
(
3
,
0x07
,
0
),
F3
(~
3
, ~
0x07
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x07
,
0
),
F3
(~
3
, ~
0x07
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
0
,
v6
},
/* std d,[rs1+%g0] */
{
"std"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
),
"d,[1+i]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
),
"d,[i+1]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
)|
RS1_G0
,
"d,[i]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
0
,
v6
},
/* std d,[rs1+0] */
{
"std"
,
F3
(
3
,
0x26
,
0
),
F3
(~
3
, ~
0x26
, ~
0
)|
ASI
(~
0
),
"q,[1+2]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x26
,
0
),
F3
(~
3
, ~
0x26
, ~
0
)|
ASI_RS2
(~
0
),
"q,[1]"
,
0
,
v6notv9
},
/* std d,[rs1+%g0] */
{
"std"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
),
"q,[1+i]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
),
"q,[i+1]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
)|
RS1_G0
,
"q,[i]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
)|
SIMM13
(~
0
),
"q,[1]"
,
0
,
v6notv9
},
/* std d,[rs1+0] */
{
"std"
,
F3
(
3
,
0x27
,
0
),
F3
(~
3
, ~
0x27
, ~
0
)|
ASI
(~
0
),
"H,[1+2]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x27
,
0
),
F3
(~
3
, ~
0x27
, ~
0
)|
ASI_RS2
(~
0
),
"H,[1]"
,
0
,
v6
},
/* std d,[rs1+%g0] */
{
"std"
,
F3
(
3
,
0x27
,
1
),
F3
(~
3
, ~
0x27
, ~
1
),
"H,[1+i]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x27
,
1
),
F3
(~
3
, ~
0x27
, ~
1
),
"H,[i+1]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x27
,
1
),
F3
(~
3
, ~
0x27
, ~
1
)|
RS1_G0
,
"H,[i]"
,
0
,
v6
},
{
"std"
,
F3
(
3
,
0x27
,
1
),
F3
(~
3
, ~
0x27
, ~
1
)|
SIMM13
(~
0
),
"H,[1]"
,
0
,
v6
},
/* std d,[rs1+0] */
{
"std"
,
F3
(
3
,
0x36
,
0
),
F3
(~
3
, ~
0x36
, ~
0
)|
ASI
(~
0
),
"Q,[1+2]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x36
,
0
),
F3
(~
3
, ~
0x36
, ~
0
)|
ASI_RS2
(~
0
),
"Q,[1]"
,
0
,
v6notv9
},
/* std d,[rs1+%g0] */
{
"std"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
),
"Q,[1+i]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
),
"Q,[i+1]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
)|
RS1_G0
,
"Q,[i]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
)|
SIMM13
(~
0
),
"Q,[1]"
,
0
,
v6notv9
},
/* std d,[rs1+0] */
{
"std"
,
F3
(
3
,
0x37
,
0
),
F3
(~
3
, ~
0x37
, ~
0
)|
ASI
(~
0
),
"D,[1+2]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x37
,
0
),
F3
(~
3
, ~
0x37
, ~
0
)|
ASI_RS2
(~
0
),
"D,[1]"
,
0
,
v6notv9
},
/* std d,[rs1+%g0] */
{
"std"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
),
"D,[1+i]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
),
"D,[i+1]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
)|
RS1_G0
,
"D,[i]"
,
0
,
v6notv9
},
{
"std"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
)|
SIMM13
(~
0
),
"D,[1]"
,
0
,
v6notv9
},
/* std d,[rs1+0] */
{
"spilld"
,
F3
(
3
,
0x07
,
0
),
F3
(~
3
, ~
0x07
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v6
},
{
"spilld"
,
F3
(
3
,
0x07
,
0
),
F3
(~
3
, ~
0x07
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* std d,[rs1+%g0] */
{
"spilld"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v6
},
{
"spilld"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v6
},
{
"spilld"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v6
},
{
"spilld"
,
F3
(
3
,
0x07
,
1
),
F3
(~
3
, ~
0x07
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* std d,[rs1+0] */
{
"stda"
,
F3
(
3
,
0x17
,
0
),
F3
(~
3
, ~
0x17
, ~
0
),
"d,[1+2]A"
,
0
,
v6
},
{
"stda"
,
F3
(
3
,
0x17
,
0
),
F3
(~
3
, ~
0x17
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
0
,
v6
},
/* stda d,[rs1+%g0] */
{
"stda"
,
F3
(
3
,
0x17
,
1
),
F3
(~
3
, ~
0x17
, ~
1
),
"d,[1+i]o"
,
0
,
v9
},
{
"stda"
,
F3
(
3
,
0x17
,
1
),
F3
(~
3
, ~
0x17
, ~
1
),
"d,[i+1]o"
,
0
,
v9
},
{
"stda"
,
F3
(
3
,
0x17
,
1
),
F3
(~
3
, ~
0x17
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
0
,
v9
},
{
"stda"
,
F3
(
3
,
0x17
,
1
),
F3
(~
3
, ~
0x17
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
0
,
v9
},
/* std d,[rs1+0] */
{
"stda"
,
F3
(
3
,
0x37
,
0
),
F3
(~
3
, ~
0x37
, ~
0
),
"H,[1+2]A"
,
0
,
v9
},
{
"stda"
,
F3
(
3
,
0x37
,
0
),
F3
(~
3
, ~
0x37
, ~
0
)|
RS2
(~
0
),
"H,[1]A"
,
0
,
v9
},
/* stda d,[rs1+%g0] */
{
"stda"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
),
"H,[1+i]o"
,
0
,
v9
},
{
"stda"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
),
"H,[i+1]o"
,
0
,
v9
},
{
"stda"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
)|
RS1_G0
,
"H,[i]o"
,
0
,
v9
},
{
"stda"
,
F3
(
3
,
0x37
,
1
),
F3
(~
3
, ~
0x37
, ~
1
)|
SIMM13
(~
0
),
"H,[1]o"
,
0
,
v9
},
/* std d,[rs1+0] */
{
"sth"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
0
,
v6
},
{
"sth"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
0
,
v6
},
/* sth d,[rs1+%g0] */
{
"sth"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
),
"d,[1+i]"
,
0
,
v6
},
{
"sth"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
),
"d,[i+1]"
,
0
,
v6
},
{
"sth"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
RS1_G0
,
"d,[i]"
,
0
,
v6
},
{
"sth"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
0
,
v6
},
/* sth d,[rs1+0] */
{
"stsh"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v6
},
{
"stsh"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* sth d,[rs1+%g0] */
{
"stsh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v6
},
{
"stsh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v6
},
{
"stsh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v6
},
{
"stsh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* sth d,[rs1+0] */
{
"stuh"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
F_ALIAS
,
v6
},
{
"stuh"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* sth d,[rs1+%g0] */
{
"stuh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
),
"d,[1+i]"
,
F_ALIAS
,
v6
},
{
"stuh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
),
"d,[i+1]"
,
F_ALIAS
,
v6
},
{
"stuh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
RS1_G0
,
"d,[i]"
,
F_ALIAS
,
v6
},
{
"stuh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
F_ALIAS
,
v6
},
/* sth d,[rs1+0] */
{
"stha"
,
F3
(
3
,
0x16
,
0
),
F3
(~
3
, ~
0x16
, ~
0
),
"d,[1+2]A"
,
0
,
v6
},
{
"stha"
,
F3
(
3
,
0x16
,
0
),
F3
(~
3
, ~
0x16
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
0
,
v6
},
/* stha ,[rs1+%g0] */
{
"stha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
),
"d,[1+i]o"
,
0
,
v9
},
{
"stha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
),
"d,[i+1]o"
,
0
,
v9
},
{
"stha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
0
,
v9
},
{
"stha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
0
,
v9
},
/* sth d,[rs1+0] */
{
"stsha"
,
F3
(
3
,
0x16
,
0
),
F3
(~
3
, ~
0x16
, ~
0
),
"d,[1+2]A"
,
F_ALIAS
,
v6
},
{
"stsha"
,
F3
(
3
,
0x16
,
0
),
F3
(~
3
, ~
0x16
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
F_ALIAS
,
v6
},
/* stha ,[rs1+%g0] */
{
"stsha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
),
"d,[1+i]o"
,
F_ALIAS
,
v9
},
{
"stsha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
),
"d,[i+1]o"
,
F_ALIAS
,
v9
},
{
"stsha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
F_ALIAS
,
v9
},
{
"stsha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
F_ALIAS
,
v9
},
/* sth d,[rs1+0] */
{
"stuha"
,
F3
(
3
,
0x16
,
0
),
F3
(~
3
, ~
0x16
, ~
0
),
"d,[1+2]A"
,
F_ALIAS
,
v6
},
{
"stuha"
,
F3
(
3
,
0x16
,
0
),
F3
(~
3
, ~
0x16
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
F_ALIAS
,
v6
},
/* stha ,[rs1+%g0] */
{
"stuha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
),
"d,[1+i]o"
,
F_ALIAS
,
v9
},
{
"stuha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
),
"d,[i+1]o"
,
F_ALIAS
,
v9
},
{
"stuha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
F_ALIAS
,
v9
},
{
"stuha"
,
F3
(
3
,
0x16
,
1
),
F3
(~
3
, ~
0x16
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
F_ALIAS
,
v9
},
/* sth d,[rs1+0] */
{
"stx"
,
F3
(
3
,
0x0e
,
0
),
F3
(~
3
, ~
0x0e
, ~
0
)|
ASI
(~
0
),
"d,[1+2]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x0e
,
0
),
F3
(~
3
, ~
0x0e
, ~
0
)|
ASI_RS2
(~
0
),
"d,[1]"
,
0
,
v9
},
/* stx d,[rs1+%g0] */
{
"stx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
),
"d,[1+i]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
),
"d,[i+1]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
)|
RS1_G0
,
"d,[i]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
)|
SIMM13
(~
0
),
"d,[1]"
,
0
,
v9
},
/* stx d,[rs1+0] */
{
"stx"
,
F3
(
3
,
0x25
,
0
)|
RD
(
1
),
F3
(~
3
, ~
0x25
, ~
0
)|
ASI
(~
0
)|
RD
(~
1
),
"F,[1+2]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x25
,
0
)|
RD
(
1
),
F3
(~
3
, ~
0x25
, ~
0
)|
ASI_RS2
(~
0
)|
RD
(~
1
),
"F,[1]"
,
0
,
v9
},
/* stx d,[rs1+%g0] */
{
"stx"
,
F3
(
3
,
0x25
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
RD
(~
1
),
"F,[1+i]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x25
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
RD
(~
1
),
"F,[i+1]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x25
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
RS1_G0
|
RD
(~
1
),
"F,[i]"
,
0
,
v9
},
{
"stx"
,
F3
(
3
,
0x25
,
1
)|
RD
(
1
),
F3
(~
3
, ~
0x25
, ~
1
)|
SIMM13
(~
0
)|
RD
(~
1
),
"F,[1]"
,
0
,
v9
},
/* stx d,[rs1+0] */
{
"stxa"
,
F3
(
3
,
0x1e
,
0
),
F3
(~
3
, ~
0x1e
, ~
0
),
"d,[1+2]A"
,
0
,
v9
},
{
"stxa"
,
F3
(
3
,
0x1e
,
0
),
F3
(~
3
, ~
0x1e
, ~
0
)|
RS2
(~
0
),
"d,[1]A"
,
0
,
v9
},
/* stxa d,[rs1+%g0] */
{
"stxa"
,
F3
(
3
,
0x1e
,
1
),
F3
(~
3
, ~
0x1e
, ~
1
),
"d,[1+i]o"
,
0
,
v9
},
{
"stxa"
,
F3
(
3
,
0x1e
,
1
),
F3
(~
3
, ~
0x1e
, ~
1
),
"d,[i+1]o"
,
0
,
v9
},
{
"stxa"
,
F3
(
3
,
0x1e
,
1
),
F3
(~
3
, ~
0x1e
, ~
1
)|
RS1_G0
,
"d,[i]o"
,
0
,
v9
},
{
"stxa"
,
F3
(
3
,
0x1e
,
1
),
F3
(~
3
, ~
0x1e
, ~
1
)|
SIMM13
(~
0
),
"d,[1]o"
,
0
,
v9
},
/* stx d,[rs1+0] */
{
"stq"
,
F3
(
3
,
0x26
,
0
),
F3
(~
3
, ~
0x26
, ~
0
)|
ASI
(~
0
),
"J,[1+2]"
,
0
,
v9
},
{
"stq"
,
F3
(
3
,
0x26
,
0
),
F3
(~
3
, ~
0x26
, ~
0
)|
ASI_RS2
(~
0
),
"J,[1]"
,
0
,
v9
},
/* stq [rs1+%g0] */
{
"stq"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
),
"J,[1+i]"
,
0
,
v9
},
{
"stq"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
),
"J,[i+1]"
,
0
,
v9
},
{
"stq"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
)|
RS1_G0
,
"J,[i]"
,
0
,
v9
},
{
"stq"
,
F3
(
3
,
0x26
,
1
),
F3
(~
3
, ~
0x26
, ~
1
)|
SIMM13
(~
0
),
"J,[1]"
,
0
,
v9
},
/* stq [rs1+0] */
{
"stqa"
,
F3
(
3
,
0x36
,
0
),
F3
(~
3
, ~
0x36
, ~
0
)|
ASI
(~
0
),
"J,[1+2]A"
,
0
,
v9
},
{
"stqa"
,
F3
(
3
,
0x36
,
0
),
F3
(~
3
, ~
0x36
, ~
0
)|
ASI_RS2
(~
0
),
"J,[1]A"
,
0
,
v9
},
/* stqa [rs1+%g0] */
{
"stqa"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
),
"J,[1+i]o"
,
0
,
v9
},
{
"stqa"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
),
"J,[i+1]o"
,
0
,
v9
},
{
"stqa"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
)|
RS1_G0
,
"J,[i]o"
,
0
,
v9
},
{
"stqa"
,
F3
(
3
,
0x36
,
1
),
F3
(~
3
, ~
0x36
, ~
1
)|
SIMM13
(~
0
),
"J,[1]o"
,
0
,
v9
},
/* stqa [rs1+0] */
{
"swap"
,
F3
(
3
,
0x0f
,
0
),
F3
(~
3
, ~
0x0f
, ~
0
)|
ASI
(~
0
),
"[1+2],d"
,
0
,
v7
},
{
"swap"
,
F3
(
3
,
0x0f
,
0
),
F3
(~
3
, ~
0x0f
, ~
0
)|
ASI_RS2
(~
0
),
"[1],d"
,
0
,
v7
},
/* swap [rs1+%g0],d */
{
"swap"
,
F3
(
3
,
0x0f
,
1
),
F3
(~
3
, ~
0x0f
, ~
1
),
"[1+i],d"
,
0
,
v7
},
{
"swap"
,
F3
(
3
,
0x0f
,
1
),
F3
(~
3
, ~
0x0f
, ~
1
),
"[i+1],d"
,
0
,
v7
},
{
"swap"
,
F3
(
3
,
0x0f
,
1
),
F3
(~
3
, ~
0x0f
, ~
1
)|
RS1_G0
,
"[i],d"
,
0
,
v7
},
{
"swap"
,
F3
(
3
,
0x0f
,
1
),
F3
(~
3
, ~
0x0f
, ~
1
)|
SIMM13
(~
0
),
"[1],d"
,
0
,
v7
},
/* swap [rs1+0],d */
{
"swapa"
,
F3
(
3
,
0x1f
,
0
),
F3
(~
3
, ~
0x1f
, ~
0
),
"[1+2]A,d"
,
0
,
v7
},
{
"swapa"
,
F3
(
3
,
0x1f
,
0
),
F3
(~
3
, ~
0x1f
, ~
0
)|
RS2
(~
0
),
"[1]A,d"
,
0
,
v7
},
/* swapa [rs1+%g0],d */
{
"swapa"
,
F3
(
3
,
0x1f
,
1
),
F3
(~
3
, ~
0x1f
, ~
1
),
"[1+i]o,d"
,
0
,
v9
},
{
"swapa"
,
F3
(
3
,
0x1f
,
1
),
F3
(~
3
, ~
0x1f
, ~
1
),
"[i+1]o,d"
,
0
,
v9
},
{
"swapa"
,
F3
(
3
,
0x1f
,
1
),
F3
(~
3
, ~
0x1f
, ~
1
)|
RS1_G0
,
"[i]o,d"
,
0
,
v9
},
{
"swapa"
,
F3
(
3
,
0x1f
,
1
),
F3
(~
3
, ~
0x1f
, ~
1
)|
SIMM13
(~
0
),
"[1]o,d"
,
0
,
v9
},
/* swap [rs1+0],d */
{
"restore"
,
F3
(
2
,
0x3d
,
0
),
F3
(~
2
, ~
0x3d
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
v6
},
{
"restore"
,
F3
(
2
,
0x3d
,
0
),
F3
(~
2
, ~
0x3d
, ~
0
)|
RD_G0
|
RS1_G0
|
ASI_RS2
(~
0
),
""
,
0
,
v6
},
/* restore %g0,%g0,%g0 */
{
"restore"
,
F3
(
2
,
0x3d
,
1
),
F3
(~
2
, ~
0x3d
, ~
1
),
"1,i,d"
,
0
,
v6
},
{
"restore"
,
F3
(
2
,
0x3d
,
1
),
F3
(~
2
, ~
0x3d
, ~
1
)|
RD_G0
|
RS1_G0
|
SIMM13
(~
0
),
""
,
0
,
v6
},
/* restore %g0,0,%g0 */
{
"rett"
,
F3
(
2
,
0x39
,
0
),
F3
(~
2
, ~
0x39
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"1+2"
,
F_UNBR
|
F_DELAYED
,
v6
},
/* rett rs1+rs2 */
{
"rett"
,
F3
(
2
,
0x39
,
0
),
F3
(~
2
, ~
0x39
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"1"
,
F_UNBR
|
F_DELAYED
,
v6
},
/* rett rs1,%g0 */
{
"rett"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
)|
RD_G0
,
"1+i"
,
F_UNBR
|
F_DELAYED
,
v6
},
/* rett rs1+X */
{
"rett"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
)|
RD_G0
,
"i+1"
,
F_UNBR
|
F_DELAYED
,
v6
},
/* rett X+rs1 */
{
"rett"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
)|
RD_G0
|
RS1_G0
,
"i"
,
F_UNBR
|
F_DELAYED
,
v6
},
/* rett X+rs1 */
{
"rett"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
)|
RD_G0
|
RS1_G0
,
"i"
,
F_UNBR
|
F_DELAYED
,
v6
},
/* rett X */
{
"rett"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
)|
RD_G0
|
SIMM13
(~
0
),
"1"
,
F_UNBR
|
F_DELAYED
,
v6
},
/* rett rs1+0 */
{
"save"
,
F3
(
2
,
0x3c
,
0
),
F3
(~
2
, ~
0x3c
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
v6
},
{
"save"
,
F3
(
2
,
0x3c
,
1
),
F3
(~
2
, ~
0x3c
, ~
1
),
"1,i,d"
,
0
,
v6
},
{
"save"
,
0x81e00000
, ~
0x81e00000
,
""
,
F_ALIAS
,
v6
},
{
"ret"
,
F3
(
2
,
0x38
,
1
)|
RS1
(
0x1f
)|
SIMM13
(
8
),
F3
(~
2
, ~
0x38
, ~
1
)|
SIMM13
(~
8
),
""
,
F_UNBR
|
F_DELAYED
,
v6
},
/* jmpl %i7+8,%g0 */
{
"retl"
,
F3
(
2
,
0x38
,
1
)|
RS1
(
0x0f
)|
SIMM13
(
8
),
F3
(~
2
, ~
0x38
, ~
1
)|
RS1
(~
0x0f
)|
SIMM13
(~
8
),
""
,
F_UNBR
|
F_DELAYED
,
v6
},
/* jmpl %o7+8,%g0 */
{
"jmpl"
,
F3
(
2
,
0x38
,
0
),
F3
(~
2
, ~
0x38
, ~
0
)|
ASI
(~
0
),
"1+2,d"
,
F_JSR
|
F_DELAYED
,
v6
},
{
"jmpl"
,
F3
(
2
,
0x38
,
0
),
F3
(~
2
, ~
0x38
, ~
0
)|
ASI_RS2
(~
0
),
"1,d"
,
F_JSR
|
F_DELAYED
,
v6
},
/* jmpl rs1+%g0,d */
{
"jmpl"
,
F3
(
2
,
0x38
,
1
),
F3
(~
2
, ~
0x38
, ~
1
)|
SIMM13
(~
0
),
"1,d"
,
F_JSR
|
F_DELAYED
,
v6
},
/* jmpl rs1+0,d */
{
"jmpl"
,
F3
(
2
,
0x38
,
1
),
F3
(~
2
, ~
0x38
, ~
1
)|
RS1_G0
,
"i,d"
,
F_JSR
|
F_DELAYED
,
v6
},
/* jmpl %g0+i,d */
{
"jmpl"
,
F3
(
2
,
0x38
,
1
),
F3
(~
2
, ~
0x38
, ~
1
),
"1+i,d"
,
F_JSR
|
F_DELAYED
,
v6
},
{
"jmpl"
,
F3
(
2
,
0x38
,
1
),
F3
(~
2
, ~
0x38
, ~
1
),
"i+1,d"
,
F_JSR
|
F_DELAYED
,
v6
},
{
"done"
,
F3
(
2
,
0x3e
,
0
)|
RD
(
0
),
F3
(~
2
, ~
0x3e
, ~
0
)|
RD
(~
0
)|
RS1_G0
|
SIMM13
(~
0
),
""
,
0
,
v9
},
{
"retry"
,
F3
(
2
,
0x3e
,
0
)|
RD
(
1
),
F3
(~
2
, ~
0x3e
, ~
0
)|
RD
(~
1
)|
RS1_G0
|
SIMM13
(~
0
),
""
,
0
,
v9
},
{
"saved"
,
F3
(
2
,
0x31
,
0
)|
RD
(
0
),
F3
(~
2
, ~
0x31
, ~
0
)|
RD
(~
0
)|
RS1_G0
|
SIMM13
(~
0
),
""
,
0
,
v9
},
{
"restored"
,
F3
(
2
,
0x31
,
0
)|
RD
(
1
),
F3
(~
2
, ~
0x31
, ~
0
)|
RD
(~
1
)|
RS1_G0
|
SIMM13
(~
0
),
""
,
0
,
v9
},
{
"sir"
,
F3
(
2
,
0x30
,
1
)|
RD
(
0xf
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
0xf
)|
RS1_G0
,
"i"
,
0
,
v9
},
{
"flush"
,
F3
(
2
,
0x3b
,
0
),
F3
(~
2
, ~
0x3b
, ~
0
)|
ASI
(~
0
),
"1+2"
,
0
,
v8
},
{
"flush"
,
F3
(
2
,
0x3b
,
0
),
F3
(~
2
, ~
0x3b
, ~
0
)|
ASI_RS2
(~
0
),
"1"
,
0
,
v8
},
/* flush rs1+%g0 */
{
"flush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
)|
SIMM13
(~
0
),
"1"
,
0
,
v8
},
/* flush rs1+0 */
{
"flush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
)|
RS1_G0
,
"i"
,
0
,
v8
},
/* flush %g0+i */
{
"flush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
),
"1+i"
,
0
,
v8
},
{
"flush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
),
"i+1"
,
0
,
v8
},
/* IFLUSH was renamed to FLUSH in v8. */
{
"iflush"
,
F3
(
2
,
0x3b
,
0
),
F3
(~
2
, ~
0x3b
, ~
0
)|
ASI
(~
0
),
"1+2"
,
F_ALIAS
,
v6
},
{
"iflush"
,
F3
(
2
,
0x3b
,
0
),
F3
(~
2
, ~
0x3b
, ~
0
)|
ASI_RS2
(~
0
),
"1"
,
F_ALIAS
,
v6
},
/* flush rs1+%g0 */
{
"iflush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
)|
SIMM13
(~
0
),
"1"
,
F_ALIAS
,
v6
},
/* flush rs1+0 */
{
"iflush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
)|
RS1_G0
,
"i"
,
F_ALIAS
,
v6
},
{
"iflush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
),
"1+i"
,
F_ALIAS
,
v6
},
{
"iflush"
,
F3
(
2
,
0x3b
,
1
),
F3
(~
2
, ~
0x3b
, ~
1
),
"i+1"
,
F_ALIAS
,
v6
},
{
"return"
,
F3
(
2
,
0x39
,
0
),
F3
(~
2
, ~
0x39
, ~
0
)|
ASI
(~
0
),
"1+2"
,
0
,
v9
},
{
"return"
,
F3
(
2
,
0x39
,
0
),
F3
(~
2
, ~
0x39
, ~
0
)|
ASI_RS2
(~
0
),
"1"
,
0
,
v9
},
/* return rs1+%g0 */
{
"return"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
)|
SIMM13
(~
0
),
"1"
,
0
,
v9
},
/* return rs1+0 */
{
"return"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
)|
RS1_G0
,
"i"
,
0
,
v9
},
/* return %g0+i */
{
"return"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
),
"1+i"
,
0
,
v9
},
{
"return"
,
F3
(
2
,
0x39
,
1
),
F3
(~
2
, ~
0x39
, ~
1
),
"i+1"
,
0
,
v9
},
{
"flushw"
,
F3
(
2
,
0x2b
,
0
),
F3
(~
2
, ~
0x2b
, ~
0
)|
RD_G0
|
RS1_G0
|
ASI_RS2
(~
0
),
""
,
0
,
v9
},
{
"membar"
,
F3
(
2
,
0x28
,
1
)|
RS1
(
0xf
),
F3
(~
2
, ~
0x28
, ~
1
)|
RD_G0
|
RS1
(~
0xf
)|
SIMM13
(~
127
),
"K"
,
0
,
v9
},
{
"stbar"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
0xf
),
F3
(~
2
, ~
0x28
, ~
0
)|
RD_G0
|
RS1
(~
0xf
)|
SIMM13
(~
0
),
""
,
0
,
v8
},
{
"prefetch"
,
F3
(
3
,
0x2d
,
0
),
F3
(~
3
, ~
0x2d
, ~
0
),
"[1+2],*"
,
0
,
v9
},
{
"prefetch"
,
F3
(
3
,
0x2d
,
0
),
F3
(~
3
, ~
0x2d
, ~
0
)|
RS2_G0
,
"[1],*"
,
0
,
v9
},
/* prefetch [rs1+%g0],prefetch_fcn */
{
"prefetch"
,
F3
(
3
,
0x2d
,
1
),
F3
(~
3
, ~
0x2d
, ~
1
),
"[1+i],*"
,
0
,
v9
},
{
"prefetch"
,
F3
(
3
,
0x2d
,
1
),
F3
(~
3
, ~
0x2d
, ~
1
),
"[i+1],*"
,
0
,
v9
},
{
"prefetch"
,
F3
(
3
,
0x2d
,
1
),
F3
(~
3
, ~
0x2d
, ~
1
)|
RS1_G0
,
"[i],*"
,
0
,
v9
},
{
"prefetch"
,
F3
(
3
,
0x2d
,
1
),
F3
(~
3
, ~
0x2d
, ~
1
)|
SIMM13
(~
0
),
"[1],*"
,
0
,
v9
},
/* prefetch [rs1+0],prefetch_fcn */
{
"prefetcha"
,
F3
(
3
,
0x3d
,
0
),
F3
(~
3
, ~
0x3d
, ~
0
),
"[1+2]A,*"
,
0
,
v9
},
{
"prefetcha"
,
F3
(
3
,
0x3d
,
0
),
F3
(~
3
, ~
0x3d
, ~
0
)|
RS2_G0
,
"[1]A,*"
,
0
,
v9
},
/* prefetcha [rs1+%g0],prefetch_fcn */
{
"prefetcha"
,
F3
(
3
,
0x3d
,
1
),
F3
(~
3
, ~
0x3d
, ~
1
),
"[1+i]o,*"
,
0
,
v9
},
{
"prefetcha"
,
F3
(
3
,
0x3d
,
1
),
F3
(~
3
, ~
0x3d
, ~
1
),
"[i+1]o,*"
,
0
,
v9
},
{
"prefetcha"
,
F3
(
3
,
0x3d
,
1
),
F3
(~
3
, ~
0x3d
, ~
1
)|
RS1_G0
,
"[i]o,*"
,
0
,
v9
},
{
"prefetcha"
,
F3
(
3
,
0x3d
,
1
),
F3
(~
3
, ~
0x3d
, ~
1
)|
SIMM13
(~
0
),
"[1]o,*"
,
0
,
v9
},
/* prefetcha [rs1+0],d */
{
"sll"
,
F3
(
2
,
0x25
,
0
),
F3
(~
2
, ~
0x25
, ~
0
)|(
1
<<
12
)|(
0x7f
<<
5
),
"1,2,d"
,
0
,
v6
},
{
"sll"
,
F3
(
2
,
0x25
,
1
),
F3
(~
2
, ~
0x25
, ~
1
)|(
1
<<
12
)|(
0x7f
<<
5
),
"1,X,d"
,
0
,
v6
},
{
"sra"
,
F3
(
2
,
0x27
,
0
),
F3
(~
2
, ~
0x27
, ~
0
)|(
1
<<
12
)|(
0x7f
<<
5
),
"1,2,d"
,
0
,
v6
},
{
"sra"
,
F3
(
2
,
0x27
,
1
),
F3
(~
2
, ~
0x27
, ~
1
)|(
1
<<
12
)|(
0x7f
<<
5
),
"1,X,d"
,
0
,
v6
},
{
"srl"
,
F3
(
2
,
0x26
,
0
),
F3
(~
2
, ~
0x26
, ~
0
)|(
1
<<
12
)|(
0x7f
<<
5
),
"1,2,d"
,
0
,
v6
},
{
"srl"
,
F3
(
2
,
0x26
,
1
),
F3
(~
2
, ~
0x26
, ~
1
)|(
1
<<
12
)|(
0x7f
<<
5
),
"1,X,d"
,
0
,
v6
},
{
"sllx"
,
F3
(
2
,
0x25
,
0
)|(
1
<<
12
),
F3
(~
2
, ~
0x25
, ~
0
)|(
0x7f
<<
5
),
"1,2,d"
,
0
,
v9
},
{
"sllx"
,
F3
(
2
,
0x25
,
1
)|(
1
<<
12
),
F3
(~
2
, ~
0x25
, ~
1
)|(
0x3f
<<
6
),
"1,Y,d"
,
0
,
v9
},
{
"srax"
,
F3
(
2
,
0x27
,
0
)|(
1
<<
12
),
F3
(~
2
, ~
0x27
, ~
0
)|(
0x7f
<<
5
),
"1,2,d"
,
0
,
v9
},
{
"srax"
,
F3
(
2
,
0x27
,
1
)|(
1
<<
12
),
F3
(~
2
, ~
0x27
, ~
1
)|(
0x3f
<<
6
),
"1,Y,d"
,
0
,
v9
},
{
"srlx"
,
F3
(
2
,
0x26
,
0
)|(
1
<<
12
),
F3
(~
2
, ~
0x26
, ~
0
)|(
0x7f
<<
5
),
"1,2,d"
,
0
,
v9
},
{
"srlx"
,
F3
(
2
,
0x26
,
1
)|(
1
<<
12
),
F3
(~
2
, ~
0x26
, ~
1
)|(
0x3f
<<
6
),
"1,Y,d"
,
0
,
v9
},
{
"mulscc"
,
F3
(
2
,
0x24
,
0
),
F3
(~
2
, ~
0x24
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
v6
},
{
"mulscc"
,
F3
(
2
,
0x24
,
1
),
F3
(~
2
, ~
0x24
, ~
1
),
"1,i,d"
,
0
,
v6
},
{
"divscc"
,
F3
(
2
,
0x1d
,
0
),
F3
(~
2
, ~
0x1d
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
sparclite
},
{
"divscc"
,
F3
(
2
,
0x1d
,
1
),
F3
(~
2
, ~
0x1d
, ~
1
),
"1,i,d"
,
0
,
sparclite
},
{
"scan"
,
F3
(
2
,
0x2c
,
0
),
F3
(~
2
, ~
0x2c
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
sparclet
|
sparclite
},
{
"scan"
,
F3
(
2
,
0x2c
,
1
),
F3
(~
2
, ~
0x2c
, ~
1
),
"1,i,d"
,
0
,
sparclet
|
sparclite
},
{
"popc"
,
F3
(
2
,
0x2e
,
0
),
F3
(~
2
, ~
0x2e
, ~
0
)|
RS1_G0
|
ASI
(~
0
),
"2,d"
,
0
,
v9
},
{
"popc"
,
F3
(
2
,
0x2e
,
1
),
F3
(~
2
, ~
0x2e
, ~
1
)|
RS1_G0
,
"i,d"
,
0
,
v9
},
{
"clr"
,
F3
(
2
,
0x02
,
0
),
F3
(~
2
, ~
0x02
, ~
0
)|
RD_G0
|
RS1_G0
|
ASI_RS2
(~
0
),
"d"
,
F_ALIAS
,
v6
},
/* or %g0,%g0,d */
{
"clr"
,
F3
(
2
,
0x02
,
1
),
F3
(~
2
, ~
0x02
, ~
1
)|
RS1_G0
|
SIMM13
(~
0
),
"d"
,
F_ALIAS
,
v6
},
/* or %g0,0,d */
{
"clr"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"[1+2]"
,
F_ALIAS
,
v6
},
{
"clr"
,
F3
(
3
,
0x04
,
0
),
F3
(~
3
, ~
0x04
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"[1]"
,
F_ALIAS
,
v6
},
/* st %g0,[rs1+%g0] */
{
"clr"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RD_G0
,
"[1+i]"
,
F_ALIAS
,
v6
},
{
"clr"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RD_G0
,
"[i+1]"
,
F_ALIAS
,
v6
},
{
"clr"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RD_G0
|
RS1_G0
,
"[i]"
,
F_ALIAS
,
v6
},
{
"clr"
,
F3
(
3
,
0x04
,
1
),
F3
(~
3
, ~
0x04
, ~
1
)|
RD_G0
|
SIMM13
(~
0
),
"[1]"
,
F_ALIAS
,
v6
},
/* st %g0,[rs1+0] */
{
"clrb"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"[1+2]"
,
F_ALIAS
,
v6
},
{
"clrb"
,
F3
(
3
,
0x05
,
0
),
F3
(~
3
, ~
0x05
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"[1]"
,
F_ALIAS
,
v6
},
/* stb %g0,[rs1+%g0] */
{
"clrb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
RD_G0
,
"[1+i]"
,
F_ALIAS
,
v6
},
{
"clrb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
RD_G0
,
"[i+1]"
,
F_ALIAS
,
v6
},
{
"clrb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
RD_G0
|
RS1_G0
,
"[i]"
,
F_ALIAS
,
v6
},
{
"clrb"
,
F3
(
3
,
0x05
,
1
),
F3
(~
3
, ~
0x05
, ~
1
)|
RD_G0
|
SIMM13
(~
0
),
"[1]"
,
F_ALIAS
,
v6
},
/* stb %g0,[rs1+0] */
{
"clrh"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"[1+2]"
,
F_ALIAS
,
v6
},
{
"clrh"
,
F3
(
3
,
0x06
,
0
),
F3
(~
3
, ~
0x06
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"[1]"
,
F_ALIAS
,
v6
},
/* sth %g0,[rs1+%g0] */
{
"clrh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
RD_G0
,
"[1+i]"
,
F_ALIAS
,
v6
},
{
"clrh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
RD_G0
,
"[i+1]"
,
F_ALIAS
,
v6
},
{
"clrh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
RD_G0
|
RS1_G0
,
"[i]"
,
F_ALIAS
,
v6
},
{
"clrh"
,
F3
(
3
,
0x06
,
1
),
F3
(~
3
, ~
0x06
, ~
1
)|
RD_G0
|
SIMM13
(~
0
),
"[1]"
,
F_ALIAS
,
v6
},
/* sth %g0,[rs1+0] */
{
"clrx"
,
F3
(
3
,
0x0e
,
0
),
F3
(~
3
, ~
0x0e
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"[1+2]"
,
F_ALIAS
,
v9
},
{
"clrx"
,
F3
(
3
,
0x0e
,
0
),
F3
(~
3
, ~
0x0e
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"[1]"
,
F_ALIAS
,
v9
},
/* stx %g0,[rs1+%g0] */
{
"clrx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
)|
RD_G0
,
"[1+i]"
,
F_ALIAS
,
v9
},
{
"clrx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
)|
RD_G0
,
"[i+1]"
,
F_ALIAS
,
v9
},
{
"clrx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
)|
RD_G0
|
RS1_G0
,
"[i]"
,
F_ALIAS
,
v9
},
{
"clrx"
,
F3
(
3
,
0x0e
,
1
),
F3
(~
3
, ~
0x0e
, ~
1
)|
RD_G0
|
SIMM13
(~
0
),
"[1]"
,
F_ALIAS
,
v9
},
/* stx %g0,[rs1+0] */
{
"orcc"
,
F3
(
2
,
0x12
,
0
),
F3
(~
2
, ~
0x12
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
v6
},
{
"orcc"
,
F3
(
2
,
0x12
,
1
),
F3
(~
2
, ~
0x12
, ~
1
),
"1,i,d"
,
0
,
v6
},
{
"orcc"
,
F3
(
2
,
0x12
,
1
),
F3
(~
2
, ~
0x12
, ~
1
),
"i,1,d"
,
0
,
v6
},
/* This is not a commutative instruction. */
{
"orncc"
,
F3
(
2
,
0x16
,
0
),
F3
(~
2
, ~
0x16
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
v6
},
{
"orncc"
,
F3
(
2
,
0x16
,
1
),
F3
(~
2
, ~
0x16
, ~
1
),
"1,i,d"
,
0
,
v6
},
/* This is not a commutative instruction. */
{
"orn"
,
F3
(
2
,
0x06
,
0
),
F3
(~
2
, ~
0x06
, ~
0
)|
ASI
(~
0
),
"1,2,d"
,
0
,
v6
},
{
"orn"
,
F3
(
2
,
0x06
,
1
),
F3
(~
2
, ~
0x06
, ~
1
),
"1,i,d"
,
0
,
v6
},
{
"tst"
,
F3
(
2
,
0x12
,
0
),
F3
(~
2
, ~
0x12
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"1"
,
0
,
v6
},
/* orcc rs1, %g0, %g0 */
{
"tst"
,
F3
(
2
,
0x12
,
0
),
F3
(~
2
, ~
0x12
, ~
0
)|
RD_G0
|
RS1_G0
|
ASI
(~
0
),
"2"
,
0
,
v6
},
/* orcc %g0, rs2, %g0 */
{
"tst"
,
F3
(
2
,
0x12
,
1
),
F3
(~
2
, ~
0x12
, ~
1
)|
RD_G0
|
SIMM13
(~
0
),
"1"
,
0
,
v6
},
/* orcc rs1, 0, %g0 */
{
"wr"
,
F3
(
2
,
0x30
,
0
),
F3
(~
2
, ~
0x30
, ~
0
)|
ASI
(~
0
),
"1,2,m"
,
0
,
v8
},
/* wr r,r,%asrX */
{
"wr"
,
F3
(
2
,
0x30
,
1
),
F3
(~
2
, ~
0x30
, ~
1
),
"1,i,m"
,
0
,
v8
},
/* wr r,i,%asrX */
{
"wr"
,
F3
(
2
,
0x30
,
0
),
F3
(~
2
, ~
0x30
, ~
0
)|
ASI_RS2
(~
0
),
"1,m"
,
F_ALIAS
,
v8
},
/* wr rs1,%g0,%asrX */
{
"wr"
,
F3
(
2
,
0x30
,
0
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"1,2,y"
,
0
,
v6
},
/* wr r,r,%y */
{
"wr"
,
F3
(
2
,
0x30
,
1
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD_G0
,
"1,i,y"
,
0
,
v6
},
/* wr r,i,%y */
{
"wr"
,
F3
(
2
,
0x30
,
0
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"1,y"
,
F_ALIAS
,
v6
},
/* wr rs1,%g0,%y */
{
"wr"
,
F3
(
2
,
0x31
,
0
),
F3
(~
2
, ~
0x31
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"1,2,p"
,
0
,
v6notv9
},
/* wr r,r,%psr */
{
"wr"
,
F3
(
2
,
0x31
,
1
),
F3
(~
2
, ~
0x31
, ~
1
)|
RD_G0
,
"1,i,p"
,
0
,
v6notv9
},
/* wr r,i,%psr */
{
"wr"
,
F3
(
2
,
0x31
,
0
),
F3
(~
2
, ~
0x31
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"1,p"
,
F_ALIAS
,
v6notv9
},
/* wr rs1,%g0,%psr */
{
"wr"
,
F3
(
2
,
0x32
,
0
),
F3
(~
2
, ~
0x32
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"1,2,w"
,
0
,
v6notv9
},
/* wr r,r,%wim */
{
"wr"
,
F3
(
2
,
0x32
,
1
),
F3
(~
2
, ~
0x32
, ~
1
)|
RD_G0
,
"1,i,w"
,
0
,
v6notv9
},
/* wr r,i,%wim */
{
"wr"
,
F3
(
2
,
0x32
,
0
),
F3
(~
2
, ~
0x32
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"1,w"
,
F_ALIAS
,
v6notv9
},
/* wr rs1,%g0,%wim */
{
"wr"
,
F3
(
2
,
0x33
,
0
),
F3
(~
2
, ~
0x33
, ~
0
)|
RD_G0
|
ASI
(~
0
),
"1,2,t"
,
0
,
v6notv9
},
/* wr r,r,%tbr */
{
"wr"
,
F3
(
2
,
0x33
,
1
),
F3
(~
2
, ~
0x33
, ~
1
)|
RD_G0
,
"1,i,t"
,
0
,
v6notv9
},
/* wr r,i,%tbr */
{
"wr"
,
F3
(
2
,
0x33
,
0
),
F3
(~
2
, ~
0x33
, ~
0
)|
RD_G0
|
ASI_RS2
(~
0
),
"1,t"
,
F_ALIAS
,
v6notv9
},
/* wr rs1,%g0,%tbr */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
2
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
2
)|
ASI
(~
0
),
"1,2,E"
,
0
,
v9
},
/* wr r,r,%ccr */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
2
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
2
),
"1,i,E"
,
0
,
v9
},
/* wr r,i,%ccr */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
3
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
3
)|
ASI
(~
0
),
"1,2,o"
,
0
,
v9
},
/* wr r,r,%asi */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
3
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
3
),
"1,i,o"
,
0
,
v9
},
/* wr r,i,%asi */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
6
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
6
)|
ASI
(~
0
),
"1,2,s"
,
0
,
v9
},
/* wr r,r,%fprs */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
6
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
6
),
"1,i,s"
,
0
,
v9
},
/* wr r,i,%fprs */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
16
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
16
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%pcr */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
16
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
16
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%pcr */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
17
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
17
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%pic */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
17
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
17
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%pic */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
18
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
18
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%dcr */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
18
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
18
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%dcr */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
19
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
19
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%gsr */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
19
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
19
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%gsr */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
20
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
20
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%set_softint */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
20
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
20
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%set_softint */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
21
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
21
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%clear_softint */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
21
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
21
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%clear_softint */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
22
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
22
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%softint */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
22
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
22
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%softint */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
23
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
23
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9a
},
/* wr r,r,%tick_cmpr */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
23
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
23
),
"1,i,_"
,
0
,
v9a
},
/* wr r,i,%tick_cmpr */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
24
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
24
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9b
},
/* wr r,r,%sys_tick */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
24
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
24
),
"1,i,_"
,
0
,
v9b
},
/* wr r,i,%sys_tick */
{
"wr"
,
F3
(
2
,
0x30
,
0
)|
RD
(
25
),
F3
(~
2
, ~
0x30
, ~
0
)|
RD
(~
25
)|
ASI
(~
0
),
"1,2,_"
,
0
,
v9b
},
/* wr r,r,%sys_tick_cmpr */
{
"wr"
,
F3
(
2
,
0x30
,
1
)|
RD
(
25
),
F3
(~
2
, ~
0x30
, ~
1
)|
RD
(~
25
),
"1,i,_"
,
0
,
v9b
},
/* wr r,i,%sys_tick_cmpr */
{
"rd"
,
F3
(
2
,
0x28
,
0
),
F3
(~
2
, ~
0x28
, ~
0
)|
SIMM13
(~
0
),
"M,d"
,
0
,
v8
},
/* rd %asrX,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1_G0
|
SIMM13
(~
0
),
"y,d"
,
0
,
v6
},
/* rd %y,r */
{
"rd"
,
F3
(
2
,
0x29
,
0
),
F3
(~
2
, ~
0x29
, ~
0
)|
RS1_G0
|
SIMM13
(~
0
),
"p,d"
,
0
,
v6notv9
},
/* rd %psr,r */
{
"rd"
,
F3
(
2
,
0x2a
,
0
),
F3
(~
2
, ~
0x2a
, ~
0
)|
RS1_G0
|
SIMM13
(~
0
),
"w,d"
,
0
,
v6notv9
},
/* rd %wim,r */
{
"rd"
,
F3
(
2
,
0x2b
,
0
),
F3
(~
2
, ~
0x2b
, ~
0
)|
RS1_G0
|
SIMM13
(~
0
),
"t,d"
,
0
,
v6notv9
},
/* rd %tbr,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
2
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
2
)|
SIMM13
(~
0
),
"E,d"
,
0
,
v9
},
/* rd %ccr,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
3
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
3
)|
SIMM13
(~
0
),
"o,d"
,
0
,
v9
},
/* rd %asi,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
4
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
4
)|
SIMM13
(~
0
),
"W,d"
,
0
,
v9
},
/* rd %tick,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
5
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
5
)|
SIMM13
(~
0
),
"P,d"
,
0
,
v9
},
/* rd %pc,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
6
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
6
)|
SIMM13
(~
0
),
"s,d"
,
0
,
v9
},
/* rd %fprs,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
16
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
16
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9a
},
/* rd %pcr,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
17
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
17
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9a
},
/* rd %pic,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
18
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
18
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9a
},
/* rd %dcr,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
19
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
19
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9a
},
/* rd %gsr,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
22
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
22
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9a
},
/* rd %softint,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
23
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
23
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9a
},
/* rd %tick_cmpr,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
24
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
24
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9b
},
/* rd %sys_tick,r */
{
"rd"
,
F3
(
2
,
0x28
,
0
)|
RS1
(
25
),
F3
(~
2
, ~
0x28
, ~
0
)|
RS1
(~
25
)|
SIMM13
(~
0
),
"/,d"
,
0
,
v9b
},
/* rd %sys_tick_cmpr,r */
{
"rdpr"
,
F3
(
2
,
0x2a
,
0
),
F3
(~
2
, ~
0x2a
, ~
0
)|
SIMM13
(~
0
),
"?,d"
,
0
,
v9
},
/* rdpr %priv,r */
{
"wrpr"
,
F3
(
2
,
0x32
,
0
),
F3
(~
2
, ~
0x32
, ~
0
),
"1,2,!"
,
0
,
v9
},
/* wrpr r1,r2,%priv */
{
"wrpr"
,
F3
(
2
,
0x32
,
0
),
F3
(~
2
, ~
0x32
, ~
0
)|
SIMM13
(~
0
),
"1,!"
,
0
,
v9
},
/* wrpr r1,%priv */
{
"wrpr"
,
F3
(
2
,
0x32
,
1
),
F3
(~
2
, ~
0x32
, ~
1
),
"1,i,!"
,
0
,
v9
},
/* wrpr r1,i,%priv */
{
"wrpr"
,
F3
(
2
,
0x32
,
1
),
F3
(~
2
, ~
0x32
, ~
1
),
"i,1,!"
,
F_ALIAS
,
v9
},
/* wrpr i,r1,%priv */
{
"wrpr"
,
F3
(
2
,
0x32
,
1
),
F3
(~
2
, ~
0x32
, ~
1
)|
RS1
(~
0
),
"i,!"
,
0
,
v9
},
/* wrpr i,%priv */
/* ??? This group seems wrong. A three operand move? */
{
"mov"
,
F3
(
2
,
0x30
,
0
),
F3
(~
2
, ~
0x30
, ~
0
)|
ASI
(~
0
),
"1,2,m"
,
F_ALIAS
,
v8
},
/* wr r,r,%asrX */