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@node Platform, Contributors, Maintenance, Top
@c %MENU% Describe all platform-specific facilities provided
@appendix Platform-specific facilities
@Theglibc{} can provide machine-specific functionality.
@menu
* PowerPC:: Facilities Specific to the PowerPC Architecture
* RISC-V:: Facilities Specific to the RISC-V Architecture
@end menu
@node PowerPC
@appendixsec PowerPC-specific Facilities
Facilities specific to PowerPC that are not specific to a particular
operating system are declared in @file{sys/platform/ppc.h}.
@deftypefun {uint64_t} __ppc_get_timebase (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Read the current value of the Time Base Register.
The @dfn{Time Base Register} is a 64-bit register that stores a monotonically
incremented value updated at a system-dependent frequency that may be
different from the processor frequency. More information is available in
@cite{Power ISA 2.06b - Book II - Section 5.2}.
@code{__ppc_get_timebase} uses the processor's time base facility directly
without requiring assistance from the operating system, so it is very
efficient.
@end deftypefun
@deftypefun {uint64_t} __ppc_get_timebase_freq (void)
@safety{@prelim{}@mtunsafe{@mtuinit{}}@asunsafe{@asucorrupt{:init}}@acunsafe{@acucorrupt{:init}}}
@c __ppc_get_timebase_freq=__get_timebase_freq @mtuinit @acsfd
@c __get_clockfreq @mtuinit @asucorrupt:init @acucorrupt:init @acsfd
@c the initialization of the static timebase_freq is not exactly
@c safe, because hp_timing_t cannot be atomically set up.
@c syscall:get_tbfreq ok
@c open dup @acsfd
@c read dup ok
@c memcpy dup ok
@c memmem dup ok
@c close dup @acsfd
Read the current frequency at which the Time Base Register is updated.
This frequency is not related to the processor clock or the bus clock.
It is also possible that this frequency is not constant. More information is
available in @cite{Power ISA 2.06b - Book II - Section 5.2}.
@end deftypefun
The following functions provide hints about the usage of resources that are
shared with other processors. They can be used, for example, if a program
waiting on a lock intends to divert the shared resources to be used by other
processors. More information is available in @cite{Power ISA 2.06b - Book II -
Section 3.2}.
@deftypefun {void} __ppc_yield (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Provide a hint that performance will probably be improved if shared resources
dedicated to the executing processor are released for use by other processors.
@end deftypefun
@deftypefun {void} __ppc_mdoio (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Provide a hint that performance will probably be improved if shared resources
dedicated to the executing processor are released until all outstanding storage
accesses to caching-inhibited storage have been completed.
@end deftypefun
@deftypefun {void} __ppc_mdoom (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Provide a hint that performance will probably be improved if shared resources
dedicated to the executing processor are released until all outstanding storage
accesses to cacheable storage for which the data is not in the cache have been
completed.
@end deftypefun
@deftypefun {void} __ppc_set_ppr_med (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Set the Program Priority Register to medium value (default).
The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls
the program's priority. By adjusting the PPR value the programmer may
improve system throughput by causing the system resources to be used
more efficiently, especially in contention situations.
The three unprivileged states available are covered by the functions
@code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
and @code{__ppc_set_ppc_med_low} (medium low). More information
available in @cite{Power ISA 2.06b - Book II - Section 3.1}.
@end deftypefun
@deftypefun {void} __ppc_set_ppr_low (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Set the Program Priority Register to low value.
@end deftypefun
@deftypefun {void} __ppc_set_ppr_med_low (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Set the Program Priority Register to medium low value.
@end deftypefun
Power ISA 2.07 extends the priorities that can be set to the Program Priority
Register (PPR). The following functions implement the new priority levels:
very low and medium high.
@deftypefun {void} __ppc_set_ppr_very_low (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Set the Program Priority Register to very low value.
@end deftypefun
@deftypefun {void} __ppc_set_ppr_med_high (void)
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Set the Program Priority Register to medium high value. The medium high
priority is privileged and may only be set during certain time intervals by
problem-state programs. If the program priority is medium high when the time
interval expires or if an attempt is made to set the priority to medium high
when it is not allowed, the priority is set to medium.
@end deftypefun
@node RISC-V
@appendixsec RISC-V-specific Facilities
Cache management facilities specific to RISC-V systems that implement the Linux
ABI are declared in @file{sys/cachectl.h}.
@deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags})
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Enforce ordering between stores and instruction cache fetches. The range of
addresses over which ordering is enforced is specified by @var{start} and
@var{end}. The @var{flags} argument controls the extent of this ordering, with
the default behavior (a @var{flags} value of 0) being to enforce the fence on
all threads in the current process. Setting the
@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
ordering on only the current thread is necessary. All other flag bits are
reserved.
@end deftypefun
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