From cd7ce12a027656ad3cda774454088de5a2c7fbfa Mon Sep 17 00:00:00 2001 From: "Paul A. Clarke" Date: Fri, 12 Jul 2019 20:13:58 -0500 Subject: [powerpc] fe{en,dis}ableexcept optimize bit translations The exceptions passed to fe{en,dis}ableexcept() are defined in the ABI as a bitmask, a combination of FE_INVALID, FE_OVERFLOW, etc. Within the functions, these bits must be translated to/from the corresponding enable bits in the Floating Point Status Control Register (FPSCR). This translation is currently done bit-by-bit. The compiler generates a series of conditional bit operations. Nicely, the "FE" exception bits are all a uniform offset from the FPSCR enable bits, so the bit-by-bit operation can instead be performed by a shift with appropriate masking. --- sysdeps/powerpc/fpu/feenablxcpt.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) (limited to 'sysdeps/powerpc/fpu/feenablxcpt.c') diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index dbaffdc..3b64398 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -33,16 +33,7 @@ feenableexcept (int excepts) excepts = (excepts | FE_INVALID) & ~ FE_ALL_INVALID; /* Sets the new exception mask. */ - if (excepts & FE_INEXACT) - fe.l |= (1 << (31 - FPSCR_XE)); - if (excepts & FE_DIVBYZERO) - fe.l |= (1 << (31 - FPSCR_ZE)); - if (excepts & FE_UNDERFLOW) - fe.l |= (1 << (31 - FPSCR_UE)); - if (excepts & FE_OVERFLOW) - fe.l |= (1 << (31 - FPSCR_OE)); - if (excepts & FE_INVALID) - fe.l |= (1 << (31 - FPSCR_VE)); + fe.l |= fenv_exceptions_to_reg (excepts); if (fe.l != curr.l) fesetenv_register (fe.fenv); -- cgit v1.1