From 81ecb0ee4970865cbe5d1da733c4879b999c528f Mon Sep 17 00:00:00 2001 From: "Paul A. Clarke" Date: Thu, 19 Sep 2019 11:58:46 -0500 Subject: [powerpc] Rename fegetenv_status to fegetenv_control fegetenv_status is used variously to retrieve the FPSCR exception enable bits, rounding mode bits, or both. These are referred to as the control bits in the POWER ISA. FPSCR status bits are also returned by the 'mffs' and 'mffsl' instructions, but they are uniformly ignored by all uses of fegetenv_status. Change the name to be reflective of its current and expected use. Reviewed-By: Paul E Murphy --- sysdeps/powerpc/fpu/feenablxcpt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sysdeps/powerpc/fpu/feenablxcpt.c') diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index cf670b8..43f6482 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -26,7 +26,7 @@ feenableexcept (int excepts) int result, new; /* Get current exception mask to return. */ - fe.fenv = curr.fenv = fegetenv_status (); + fe.fenv = curr.fenv = fegetenv_control (); result = fenv_reg_to_exceptions (fe.l); if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID) -- cgit v1.1