From 5744c68d78f6ca6c6500e2c8d3d85b3a31f4ed2a Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Sun, 14 Aug 2011 15:46:52 -0700 Subject: Align x86 TCB to 64 bytes (cache line size), important for Atom. --- nptl/sysdeps/i386/pthreaddef.h | 12 +++++++++--- nptl/sysdeps/x86_64/pthreaddef.h | 16 ++++++++++++---- 2 files changed, 21 insertions(+), 7 deletions(-) (limited to 'nptl/sysdeps') diff --git a/nptl/sysdeps/i386/pthreaddef.h b/nptl/sysdeps/i386/pthreaddef.h index 43b771c..1e84066 100644 --- a/nptl/sysdeps/i386/pthreaddef.h +++ b/nptl/sysdeps/i386/pthreaddef.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002, 2003 Free Software Foundation, Inc. +/* Copyright (C) 2002,2003,2011 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Ulrich Drepper , 2002. @@ -27,8 +27,14 @@ /* Minimal stack size after allocating thread descriptor and guard size. */ #define MINIMAL_REST_STACK 2048 -/* Alignment requirement for TCB. */ -#define TCB_ALIGNMENT 16 +/* Alignment requirement for TCB. + + Some processors such as Intel Atom pay a big penalty on every + access using a segment override if that segment's base is not + aligned to the size of a cache line. (See Intel 64 and IA-32 + Architectures Optimization Reference Manual, section 13.3.3.3, + "Segment Base".) On such machines, a cache line is 64 bytes. */ +#define TCB_ALIGNMENT 64 /* Location of current stack frame. */ diff --git a/nptl/sysdeps/x86_64/pthreaddef.h b/nptl/sysdeps/x86_64/pthreaddef.h index 8ec135c..9de4af2 100644 --- a/nptl/sysdeps/x86_64/pthreaddef.h +++ b/nptl/sysdeps/x86_64/pthreaddef.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc. +/* Copyright (C) 2002,2003,2007,2011 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Ulrich Drepper , 2002. @@ -27,9 +27,17 @@ /* Minimal stack size after allocating thread descriptor and guard size. */ #define MINIMAL_REST_STACK 2048 -/* Alignment requirement for TCB. Need to store post-AVX vector registers - in the TCB and we want the storage to be aligned at 32-byte. */ -#define TCB_ALIGNMENT 32 +/* Alignment requirement for TCB. + + We need to store post-AVX vector registers in the TCB and we want the + storage to be aligned to at least 32 bytes. + + Some processors such as Intel Atom pay a big penalty on every + access using a segment override if that segment's base is not + aligned to the size of a cache line. (See Intel 64 and IA-32 + Architectures Optimization Reference Manual, section 13.3.3.3, + "Segment Base".) On such machines, a cache line is 64 bytes. */ +#define TCB_ALIGNMENT 64 /* Location of current stack frame. The frame pointer is not usable. */ -- cgit v1.1