From e9dd3682963a7038d699430e3ece68045b6caafc Mon Sep 17 00:00:00 2001 From: Tejas Belagod Date: Mon, 27 Jun 2022 18:00:50 +0000 Subject: AArch64: Add asymmetric faulting mode for tag violations in mem.tagging tunable The new asymmetric mode is available when HWCAP2_MTE3 is set (support is available), bit2 is set in the tunable (user request per application), and the system is configured such that the asymmetric mode is preferred over sync or async (per-cpu system-wide setting). Reviewed-by: Szabolcs Nagy --- manual/tunables.texi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'manual') diff --git a/manual/tunables.texi b/manual/tunables.texi index 2c07601..83cdcda 100644 --- a/manual/tunables.texi +++ b/manual/tunables.texi @@ -602,6 +602,9 @@ Bit 1 enables precise faulting mode for tag violations on systems that support deferred tag violation reporting. This may cause programs to run more slowly. +Bit 2 enables either precise or deferred faulting mode for tag violations +whichever is preferred by the system. + Other bits are currently reserved. @Theglibc{} startup code will automatically enable memory tagging -- cgit v1.1