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On Skylake, it changes log1p bench performance by:
Before After Improvement
max 63.349 58.347 8%
min 4.448 5.651 -30%
mean 12.0674 10.336 14%
The minimum code path is
if (hx < 0x3FDA827A) /* x < 0.41422 */
{
if (__glibc_unlikely (ax >= 0x3ff00000)) /* x <= -1.0 */
{
...
}
if (__glibc_unlikely (ax < 0x3e200000)) /* |x| < 2**-29 */
{
math_force_eval (two54 + x); /* raise inexact */
if (ax < 0x3c900000) /* |x| < 2**-54 */
{
...
}
else
return x - x * x * 0.5;
FMA and non-FMA code sequences look similar. Non-FMA version is slightly
faster. Since log1p is called by asinh and atanh, it improves asinh
performance by:
Before After Improvement
max 75.645 63.135 16%
min 10.074 10.071 0%
mean 15.9483 14.9089 6%
and improves atanh performance by:
Before After Improvement
max 91.768 75.081 18%
min 15.548 13.883 10%
mean 18.3713 16.8011 8%
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On Skylake, it improves expm1 bench performance by:
Before After Improvement
max 70.204 68.054 3%
min 20.709 16.2 22%
mean 22.1221 16.7367 24%
NB: Add
extern long double __expm1l (long double);
extern long double __expm1f128 (long double);
for __typeof (__expm1l) and __typeof (__expm1f128) when __expm1 is
defined since __expm1 may be expanded in their declarations which
causes the build failure.
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On Skylake, it improves log2 bench performance by:
Before After Improvement
max 208.779 63.827 69%
min 9.977 6.55 34%
mean 10.366 6.8191 34%
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Sort Makefile variables using scripts/sort-makefile-lines.py.
No code generation changes observed in libm. No regressions on x86_64.
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The compiler may substitute calls to sin or cos with calls to sincos, thus
we should have the same optimized implementations for sincos. The
optimized implementations may produce results that differ, that also makes
sure that the sincos call aggrees with the sin and cos calls.
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1. Add sysdeps/x86_64/fpu/Makeconfig to auto-generate libmvec.mk, which
contains libmvec ABI test dependencies and CFLAGS, in the build directory.
2. Include libmvec.mk for libmvec ABI test dependencies and CFLAGS.
Tested on SSE4, AVX, AVX2 and AVX512 machines.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
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This patch adds support for the sse4.1 hardware floating point
roundeven.
Here is some benchmark results on my systems:
=AMD Ryzen 9 3900X 12-Core Processor=
* benchmark result before this commit
| | roundeven | roundevenf |
|------------|--------------|--------------|
| duration | 3.75587e+09 | 3.75114e+09 |
| iterations | 3.93053e+08 | 4.35402e+08 |
| max | 52.592 | 58.71 |
| min | 7.98 | 7.22 |
| mean | 9.55563 | 8.61535 |
* benchmark result after this commit
| | roundeven | roundevenf |
|------------|---------------|--------------|
| duration | 3.73815e+09 | 3.73738e+09 |
| iterations | 5.82692e+08 | 5.91498e+08 |
| max | 56.468 | 51.642 |
| min | 6.27 | 6.156 |
| mean | 6.41532 | 6.3185 |
=Intel(R) Pentium(R) CPU D1508 @ 2.20GHz=
* benchmark result before this commit
| | roundeven | roundevenf |
|------------|--------------|--------------|
| duration | 2.18208e+09 | 2.18258e+09 |
| iterations | 2.39932e+08 | 2.46924e+08 |
| max | 96.378 | 98.035 |
| min | 6.776 | 5.94 |
| mean | 9.09456 | 8.83907 |
* benchmark result after this commit
| | roundeven | roundevenf |
|------------|--------------|--------------|
| duration | 2.17415e+09 | 2.17005e+09 |
| iterations | 3.56193e+08 | 4.09824e+08 |
| max | 51.693 | 97.192 |
| min | 5.926 | 5.093 |
| mean | 6.10385 | 5.29507 |
Signed-off-by: Shen-Ta Hsieh <ibmibmibm.tw@gmail.com>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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Finally remove all mpa related files, headers, declarations, probes, unused
tables and update makefiles.
Reviewed-By: Paul Zimmermann <Paul.Zimmermann@inria.fr>
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The algorithm is exp(y * log(x)), where log(x) is computed with about
1.3*2^-68 relative error (1.5*2^-68 without fma), returning the result
in two doubles, and the exp part uses the same algorithm (and lookup
tables) as exp, but takes the input as two doubles and a sign (to handle
negative bases with odd integer exponent). The __exp1 internal symbol
is no longer necessary.
There is separate code path when fma is not available but the worst case
error is about 0.54 ULP in both cases. The lookup table and consts for
log are 4168 bytes. The .rodata+.text is decreased by 37908 bytes on
aarch64. The non-nearest rounding error is less than 1 ULP.
Improvements on Cortex-A72 compared to current glibc master:
pow thruput: 2.40x in [0.01 11.1]x[0.01 11.1]
pow latency: 1.84x in [0.01 11.1]x[0.01 11.1]
Tested on
aarch64-linux-gnu (defined __FP_FAST_FMA, TOINT_INTRINSICS) and
arm-linux-gnueabihf (!defined __FP_FAST_FMA, !TOINT_INTRINSICS) and
x86_64-linux-gnu (!defined __FP_FAST_FMA, !TOINT_INTRINSICS) and
powerpc64le-linux-gnu (defined __FP_FAST_FMA, !TOINT_INTRINSICS) targets.
* NEWS: Mention pow improvements.
* math/Makefile (type-double-routines): Add e_pow_log_data.
* sysdeps/generic/math_private.h (__exp1): Remove.
* sysdeps/i386/fpu/e_pow_log_data.c: New file.
* sysdeps/ia64/fpu/e_pow_log_data.c: New file.
* sysdeps/ieee754/dbl-64/Makefile (CFLAGS-e_pow.c): Allow fma
contraction.
* sysdeps/ieee754/dbl-64/e_exp.c (__exp1): Remove.
(exp_inline): Remove.
(__ieee754_exp): Only single double input is handled.
* sysdeps/ieee754/dbl-64/e_pow.c: Rewrite.
* sysdeps/ieee754/dbl-64/e_pow_log_data.c: New file.
* sysdeps/ieee754/dbl-64/math_config.h (issignaling_inline): Define.
(__pow_log_data): Define.
* sysdeps/ieee754/dbl-64/upow.h: Remove.
* sysdeps/ieee754/dbl-64/upow.tbl: Remove.
* sysdeps/m68k/m680x0/fpu/e_pow_log_data.c: New file.
* sysdeps/x86_64/fpu/multiarch/Makefile (CFLAGS-e_pow-fma.c): Allow fma
contraction.
(CFLAGS-e_pow-fma4.c): Likewise.
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Remove the now unused mplog and mpexp files.
* math/Makefile: Remove mpexp.c and mplog.c
* sysdeps/i386/fpu/mpexp.c: Delete file.
* sysdeps/i386/fpu/mplog.c: Likewise.
* sysdeps/ia64/fpu/mpexp.c: Likewise.
* sysdeps/ia64/fpu/mplog.c: Likewise.
* sysdeps/ieee754/dbl-64/e_exp.c: Remove mention of mpexp and mplog.
* sysdeps/ieee754/dbl-64/mpa.h (__pow_mp): Remove unused function.
* sysdeps/ieee754/dbl-64/mpexp.c: Delete file.
* sysdeps/ieee754/dbl-64/mplog.c: Likewise.
* sysdeps/m68k/m680x0/fpu/mpexp.c: Likewise.
* sysdeps/m68k/m680x0/fpu/mplog.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/Makefile: Remove mpexp* and mplog*.
* sysdeps/x86_64/fpu/multiarch/e_log-avx.c: Remove unused defines.
* sysdeps/x86_64/fpu/multiarch/e_log-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_log-fma4.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mpexp-avx.c: Delete file.
* sysdeps/x86_64/fpu/multiarch/mpexp-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mpexp-fma4.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mplog-avx.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mplog-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mplog-fma4.c: Likewise.
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Remove the __slowexp code, so exp is no longer correctly rounded. The
result is computed to about 70 bits precision so the worst case ulp
error is about 0.500007 in nearest rounding mode.
* manual/probes.texi: Remove slowexp probes.
* math/Makefile: Remove slowexp.
* sysdeps/generic/math_private.h (__slowexp): Remove.
* sysdeps/ieee754/dbl-64/e_exp.c (__ieee754_exp): Remove __slowexp and
document error bounds.
* sysdeps/i386/fpu/slowexp.c: Remove.
* sysdeps/ia64/fpu/slowexp.c: Remove.
* sysdeps/ieee754/dbl-64/slowexp.c: Remove.
* sysdeps/ieee754/dbl-64/uexp.h (err_0): Remove.
* sysdeps/m68k/m680x0/fpu/slowexp.c: Remove.
* sysdeps/powerpc/power4/fpu/Makefile (CPPFLAGS-slowexp.c): Remove.
* sysdeps/x86_64/fpu/multiarch/Makefile: Remove slowexp-fma.
* sysdeps/x86_64/fpu/multiarch/e_exp-avx.c (__slowexp): Remove.
* sysdeps/x86_64/fpu/multiarch/e_exp-fma.c (__slowexp): Remove.
* sysdeps/x86_64/fpu/multiarch/e_exp-fma4.c (__slowexp): Remove.
* sysdeps/x86_64/fpu/multiarch/slowexp-avx.c: Remove.
* sysdeps/x86_64/fpu/multiarch/slowexp-fma.c: Remove.
* sysdeps/x86_64/fpu/multiarch/slowexp-fma4.c: Remove.
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Remove the slow paths from pow. Like several other double precision math
functions, pow is exactly rounded. This is not required from math functions
and causes major overheads as it requires multiple fallbacks using higher
precision arithmetic if a result is close to 0.5ULP. Ridiculous slowdowns
of up to 100000x have been reported when the highest precision path triggers.
All GLIBC math tests pass on AArch64 and x64 (with ULP of pow set to 1).
The worst case error is ~0.506ULP. A simple test over a few hundred million
values shows pow is 10% faster on average. This fixes BZ #13932.
[BZ #13932]
* sysdeps/ieee754/dbl-64/uexp.h (err_1): Remove.
* benchtests/pow-inputs: Update comment for slow path cases.
* manual/probes.texi (slowpow_p10): Delete removed probe.
(slowpow_p10): Likewise.
* math/Makefile: Remove halfulp.c and slowpow.c.
* sysdeps/aarch64/libm-test-ulps: Set ULP of pow to 1.
* sysdeps/generic/math_private.h (__exp1): Remove error argument.
(__halfulp): Remove.
(__slowpow): Remove.
* sysdeps/i386/fpu/halfulp.c: Delete file.
* sysdeps/i386/fpu/slowpow.c: Likewise.
* sysdeps/ia64/fpu/halfulp.c: Likewise.
* sysdeps/ia64/fpu/slowpow.c: Likewise.
* sysdeps/ieee754/dbl-64/e_exp.c (__exp1): Remove error argument,
improve comments and add error analysis.
* sysdeps/ieee754/dbl-64/e_pow.c (__ieee754_pow): Add error analysis.
(power1): Remove function:
(log1): Remove error argument, add error analysis.
(my_log2): Remove function.
* sysdeps/ieee754/dbl-64/halfulp.c: Delete file.
* sysdeps/ieee754/dbl-64/slowpow.c: Likewise.
* sysdeps/m68k/m680x0/fpu/halfulp.c: Likewise.
* sysdeps/m68k/m680x0/fpu/slowpow.c: Likewise.
* sysdeps/powerpc/power4/fpu/Makefile: Remove CPPFLAGS-slowpow.c.
* sysdeps/x86_64/fpu/libm-test-ulps: Set ULP of pow to 1.
* sysdeps/x86_64/fpu/multiarch/Makefile: Remove slowpow-fma.c,
slowpow-fma4.c, halfulp-fma.c, halfulp-fma4.c.
* sysdeps/x86_64/fpu/multiarch/e_pow-fma.c (__slowpow): Remove define.
* sysdeps/x86_64/fpu/multiarch/e_pow-fma4.c (__slowpow): Likewise.
* sysdeps/x86_64/fpu/multiarch/halfulp-fma.c: Delete file.
* sysdeps/x86_64/fpu/multiarch/halfulp-fma4.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowpow-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowpow-fma4.c: Likewise.
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Since the x86-64 assembly version of sincosf is higly optimized with
vector instructions, there isn't much room for improvement. However
s_sincosf.c written in C with vector math and intrinsics can be
optimized by GCC with FMA.
On Skylake, bench-sincosf reports performance improvement:
Assembly FMA improvement
max 104.042 101.008 3%
min 9.426 8.586 10%
mean 20.6209 18.2238 13%
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add s_sincosf-sse2 and s_sincosf-fma.
(CFLAGS-s_sincosf-fma.c): New.
* sysdeps/x86_64/fpu/multiarch/s_sincosf-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/s_sincosf-sse2.S: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_sincosf.c: Likewise.
* sysdeps/x86_64/fpu/s_sincosf.S: Don't add alias if
__sincosf is defined.
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Revert:
2017-12-19 Joseph Myers <joseph@codesourcery.com>
* sysdeps/x86_64/fpu/libm-test-ulps: Update.
2017-12-19 Patrick McGehearty <patrick.mcgehearty@oracle.com>
* sysdeps/ieee754/dbl-64/e_exp.c: Include <math-svid-compat.h> and
<errno.h>. Include "eexp.tbl".
(half): New constant.
(one): Likewise.
(__ieee754_exp): Rewrite.
(__slowexp): Remove prototype.
* sysdeps/ieee754/dbl-64/eexp.tbl: New file.
* sysdeps/ieee754/dbl-64/slowexp.c: Remove file.
* sysdeps/i386/fpu/slowexp.c: Likewise.
* sysdeps/ia64/fpu/slowexp.c: Likewise.
* sysdeps/m68k/m680x0/fpu/slowexp.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowexp-avx.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowexp-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowexp-fma4.c: Likewise.
* sysdeps/generic/math_private.h (__slowexp): Remove prototype.
* sysdeps/ieee754/dbl-64/e_pow.c: Remove mention of slowexp.c in
comment.
* sysdeps/powerpc/power4/fpu/Makefile [$(subdir) = math]
(CPPFLAGS-slowexp.c): Remove variable.
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Remove slowexp-fma, slowexp-fma4 and slowexp-avx.
(CFLAGS-slowexp-fma.c): Remove variable.
(CFLAGS-slowexp-fma4.c): Likewise.
(CFLAGS-slowexp-avx.c): Likewise.
* sysdeps/x86_64/fpu/multiarch/e_exp-avx.c (__slowexp): Do not
define as macro.
* sysdeps/x86_64/fpu/multiarch/e_exp-fma.c (__slowexp): Likewise.
* sysdeps/x86_64/fpu/multiarch/e_exp-fma4.c (__slowexp): Likewise.
* math/Makefile (type-double-routines): Remove slowexp.
* manual/probes.texi (slowexp_p6): Remove.
(slowexp_p32): Likewise.
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These changes will be active for all platforms that don't provide
their own exp() routines. They will also be active for ieee754
versions of ccos, ccosh, cosh, csin, csinh, sinh, exp10, gamma, and
erf.
Typical performance gains is typically around 5x when measured on
Sparc s7 for common values between exp(1) and exp(40).
Using the glibc perf tests on sparc,
sparc (nsec) x86 (nsec)
old new old new
max 17629 395 5173 144
min 399 54 15 13
mean 5317 200 1349 23
The extreme max times for the old (ieee754) exp are due to the
multiprecision computation in the old algorithm when the true value is
very near 0.5 ulp away from an value representable in double
precision. The new algorithm does not take special measures for those
cases. The current glibc exp perf tests overrepresent those values.
Informal testing suggests approximately one in 200 cases might
invoke the high cost computation. The performance advantage of the new
algorithm for other values is still large but not as large as indicated
by the chart above.
Glibc correctness tests for exp() and expf() were run. Within the
test suite 3 input values were found to cause 1 bit differences (ulp)
when "FE_TONEAREST" rounding mode is set. No differences in exp() were
seen for the tested values for the other rounding modes.
Typical example:
exp(-0x1.760cd2p+0) (-1.46113312244415283203125)
new code: 2.31973271630014299393707e-01 0x1.db14cd799387ap-3
old code: 2.31973271630014271638132e-01 0x1.db14cd7993879p-3
exp = 2.31973271630014285508337 (high precision)
Old delta: off by 0.49 ulp
New delta: off by 0.51 ulp
In addition, because ieee754_exp() is used by other routines, cexp()
showed test results with very small imaginary input values where the
imaginary portion of the result was off by 3 ulp when in upward
rounding mode, but not in the other rounding modes. For x86, tgamma
showed a few values where the ulp increased to 6 (max ulp for tgamma
is 5). Sparc tgamma did not show these failures. I presume the tgamma
differences are due to compiler optimization differences within the
gamma function.The gamma function is known to be difficult to compute
accurately.
* sysdeps/ieee754/dbl-64/e_exp.c: Include <math-svid-compat.h> and
<errno.h>. Include "eexp.tbl".
(half): New constant.
(one): Likewise.
(__ieee754_exp): Rewrite.
(__slowexp): Remove prototype.
* sysdeps/ieee754/dbl-64/eexp.tbl: New file.
* sysdeps/ieee754/dbl-64/slowexp.c: Remove file.
* sysdeps/i386/fpu/slowexp.c: Likewise.
* sysdeps/ia64/fpu/slowexp.c: Likewise.
* sysdeps/m68k/m680x0/fpu/slowexp.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowexp-avx.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowexp-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowexp-fma4.c: Likewise.
* sysdeps/generic/math_private.h (__slowexp): Remove prototype.
* sysdeps/ieee754/dbl-64/e_pow.c: Remove mention of slowexp.c in
comment.
* sysdeps/powerpc/power4/fpu/Makefile [$(subdir) = math]
(CPPFLAGS-slowexp.c): Remove variable.
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Remove slowexp-fma, slowexp-fma4 and slowexp-avx.
(CFLAGS-slowexp-fma.c): Remove variable.
(CFLAGS-slowexp-fma4.c): Likewise.
(CFLAGS-slowexp-avx.c): Likewise.
* sysdeps/x86_64/fpu/multiarch/e_exp-avx.c (__slowexp): Do not
define as macro.
* sysdeps/x86_64/fpu/multiarch/e_exp-fma.c (__slowexp): Likewise.
* sysdeps/x86_64/fpu/multiarch/e_exp-fma4.c (__slowexp): Likewise.
* math/Makefile (type-double-routines): Remove slowexp.
* manual/probes.texi (slowexp_p6): Remove.
(slowexp_p32): Likewise.
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On Skylake, bench-cosf reports performance improvement:
Before After Improvement
max 135.362 94.552 43%
min 8.532 7.688 11%
mean 17.1446 11.8128 45%
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add s_cosf-sse2 and s_cosf-fma.
(CFLAGS-s_cosf-fma.c): New.
* sysdeps/x86_64/fpu/multiarch/s_cosf-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/s_cosf-sse2.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_cosf.c: Likewise.
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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On Skylake, bench-sinf reports performance improvement:
Before After Improvement
max 153.996 100.094 54%
min 8.546 6.852 25%
mean 18.1223 11.802 54%
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add s_sinf-sse2 and s_sinf-fma.
(CFLAGS-s_sinf-fma.c): New.
* sysdeps/x86_64/fpu/multiarch/s_sinf-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/s_sinf-sse2.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_sinf.c: Likewise.
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For workload-spec2017.wrf, on Skylake, it improves performance by:
Before After Improvement
reciprocal-throughput 35.4713 27.3842 29%
latency 82.4537 66.3175 24%
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add e_powf-fma.
(CFLAGS-e_powf-fma.c): New.
* sysdeps/x86_64/fpu/multiarch/e_powf-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/e_powf.c: Likewise.
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For workload-spec2017.wrf, on Skylake, it improves performance by:
Before After Improvement
reciprocal-throughput 16.5937 14.0789 17%
latency 41.7755 35.3586 18%
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add e_log2f-fma.
(CFLAGS-e_log2f-fma.c): New.
* sysdeps/x86_64/fpu/multiarch/e_log2f-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/e_log2f.c: Likewise.
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For workload-spec2017.wrf, on Skylake, it improves performance by:
Before After Improvement
reciprocal-throughput 16.1534 13.8874 16%
latency 41.9642 34.3072 22%
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add e_logf-fma.
(CFLAGS-e_logf-fma.c): New.
* sysdeps/x86_64/fpu/multiarch/e_logf-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/e_logf.c: Likewise.
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For workload-spec2017.wrf, on Skylake, it improves performance by:
Before After Improvement
reciprocal-throughput 13.0291 11.2225 16%
latency 44.5154 37.5766 18%
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add e_exp2f-fma.
(CFLAGS-e_exp2f-fma.c): New.
* sysdeps/x86_64/fpu/multiarch/e_exp2f-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/e_exp2f.c: Likewise.
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This patch replaces x86-64 assembly versions of e_expf with generic
e_expf.c. For workload-spec2017.wrf, on Nehalem, it improves
performance by:
Before After Improvement
reciprocal-throughput 36.039 20.7749 73%
latency 58.8096 40.8715 43%
On Skylake, it improves
Before After Improvement
reciprocal-throughput 18.4436 11.1693 65%
latency 47.5162 37.5411 26%
* sysdeps/x86_64/fpu/e_expf.S: Removed.
* sysdeps/x86_64/fpu/multiarch/e_expf-fma.S: Likewise.
* sysdeps/x86_64/fpu/w_expf.c: Likewise.
* sysdeps/x86_64/fpu/libm-test-ulps: Updated for generic
e_expf.c.
* sysdeps/x86_64/fpu/multiarch/Makefile (CFLAGS-e_expf-fma.c):
New.
* sysdeps/x86_64/fpu/multiarch/e_expf-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/e_expf.c (__redirect_ieee754_expf):
Renamed to ...
(__redirect_expf): This.
(SYMBOL_NAME): Changed to expf.
(__ieee754_expf): Renamed to ...
(__expf): This.
(__GI___expf): This.
(__ieee754_expf): Add strong_alias.
(__expf_finite): Likewise.
(__expf): New.
Include <sysdeps/ieee754/flt-32/e_expf.c>.
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|
This patch adds SSE4.1 versions of trunc and truncf, using the roundsd
/ roundss instructions, similar to the versions of ceil, floor, rint
and nearbyint functions we already have. In my testing with the glibc
benchtests these are about 30% faster than the C versions for double,
20% faster for float.
Tested for x86_64.
[BZ #20142]
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add s_trunc-c, s_truncf-c, s_trunc-sse4_1 and s_truncf-sse4_1.
* sysdeps/x86_64/fpu/multiarch/s_trunc-c.c: New file.
* sysdeps/x86_64/fpu/multiarch/s_trunc-sse4_1.S: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_trunc.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_truncf-c.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_truncf-sse4_1.S: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_truncf.c: Likewise.
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|
FMA optimized e_expf improves performance by more than 50% on Skylake.
[BZ #21912]
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add e_expf-fma.
* sysdeps/x86_64/fpu/multiarch/e_expf-fma.S: New file.
* sysdeps/x86_64/fpu/multiarch/e_expf.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/ifunc-fma.h: Likewise.
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|
This patch adds multiarch functions optimized with -mfma -mavx2 to libm.
e_pow-fma.c is compiled with $(config-cflags-nofma) due to PR 19003.
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add e_exp-fma, e_log-fma, e_pow-fma, s_atan-fma, e_asin-fma,
e_atan2-fma, s_sin-fma, s_tan-fma, mplog-fma, mpa-fma,
slowexp-fma, slowpow-fma, sincos32-fma, doasin-fma, dosincos-fma,
halfulp-fma, mpexp-fma, mpatan2-fma, mpatan-fma, mpsqrt-fma,
and mptan-fma.
(CFLAGS-doasin-fma.c): New.
(CFLAGS-dosincos-fma.c): Likewise.
(CFLAGS-e_asin-fma.c): Likewise.
(CFLAGS-e_atan2-fma.c): Likewise.
(CFLAGS-e_exp-fma.c): Likewise.
(CFLAGS-e_log-fma.c): Likewise.
(CFLAGS-e_pow-fma.c): Likewise.
(CFLAGS-halfulp-fma.c): Likewise.
(CFLAGS-mpa-fma.c): Likewise.
(CFLAGS-mpatan-fma.c): Likewise.
(CFLAGS-mpatan2-fma.c): Likewise.
(CFLAGS-mpexp-fma.c): Likewise.
(CFLAGS-mplog-fma.c): Likewise.
(CFLAGS-mpsqrt-fma.c): Likewise.
(CFLAGS-mptan-fma.c): Likewise.
(CFLAGS-s_atan-fma.c): Likewise.
(CFLAGS-sincos32-fma.c): Likewise.
(CFLAGS-slowexp-fma.c): Likewise.
(CFLAGS-slowpow-fma.c): Likewise.
(CFLAGS-s_sin-fma.c): Likewise.
(CFLAGS-s_tan-fma.c): Likewise.
* sysdeps/x86_64/fpu/multiarch/doasin-fma.c: New file.
* sysdeps/x86_64/fpu/multiarch/dosincos-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_asin-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_atan2-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_exp-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_log-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_pow-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/halfulp-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/ifunc-avx-fma4.h: Likewise.
* sysdeps/x86_64/fpu/multiarch/ifunc-fma4.h: Likewise.
* sysdeps/x86_64/fpu/multiarch/mpa-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mpatan-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mpatan2-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mpexp-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mplog-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mpsqrt-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/mptan-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_atan-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_sin-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_tan-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/sincos32-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowexp-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/slowpow-fma.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_asin.c: Rewrite.
* sysdeps/x86_64/fpu/multiarch/e_atan2.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_exp.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_log.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_pow.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_atan.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_sin.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_tan.c: Likewise.
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|
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines)
Add svml_d_cos2_core-sse2, svml_d_cos4_core-sse,
svml_d_cos8_core-avx2, svml_d_exp2_core-sse2,
svml_d_exp4_core-sse, svml_d_exp8_core-avx2,
svml_d_log2_core-sse2, svml_d_log4_core-sse,
svml_d_log8_core-avx2, svml_d_pow2_core-sse2,
svml_d_pow4_core-sse, svml_d_pow8_core-avx2
svml_d_sin2_core-sse2, svml_d_sin4_core-sse,
svml_d_sin8_core-avx2, svml_d_sincos2_core-sse2,
svml_d_sincos4_core-sse, svml_d_sincos8_core-avx2,
svml_s_cosf16_core-avx2, svml_s_cosf4_core-sse2,
svml_s_cosf8_core-sse, svml_s_expf16_core-avx2,
svml_s_expf4_core-sse2, svml_s_expf8_core-sse,
svml_s_logf16_core-avx2, svml_s_logf4_core-sse2,
svml_s_logf8_core-sse, svml_s_powf16_core-avx2,
svml_s_powf4_core-sse2, svml_s_powf8_core-sse,
svml_s_sincosf16_core-avx2, svml_s_sincosf4_core-sse2,
svml_s_sincosf8_core-sse, svml_s_sinf16_core-avx2,
svml_s_sinf4_core-sse2 and svml_s_sinf8_core-sse.
* sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-avx2.h: New file.
* sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-avx512.h: Likewise.
* sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-sse4_1.h: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf16_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_expf16_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_expf4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_expf8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_logf16_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_logf4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_logf8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_powf16_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_powf4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_powf8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf16_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf16_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf4_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf8_core.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN2v_cos): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN4v_cos): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN8v_cos): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN2v_exp): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN4v_exp): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN8v_exp): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_log2_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN2v_log): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_log4_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN4v_log): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_log8_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN8v_log): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN2vv_pow): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN4vv_pow): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN8vv_pow): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN2v_sin): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN4v_sin): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN8v_sin): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN2vvv_sincos): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN4vvv_sincos): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN8vvv_sincos): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf16_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf16_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN16v_cosf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf4_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN4v_cosf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_cosf8_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN8v_cosf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_expf16_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_expf16_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN16v_expf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_expf4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_expf4_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN4v_expf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_expf8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_expf8_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN8v_expf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_logf16_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_logf16_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN16v_logf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_logf4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_logf4_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN4v_logf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_logf8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_logf8_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN8v_logf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_powf16_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_powf16_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN16vv_powf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_powf4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_powf4_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN4vv_powf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_powf8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_powf8_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN8vv_powf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf16_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf16_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN16vvv_sincosf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf4_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN4vvv_sincosf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sincosf8_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN8vvv_sincosf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf16_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf16_core-avx2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVeN16v_sinf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf4_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf4_core-sse2.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVbN4v_sinf): Removed.
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf8_core.S: Renamed to
...
* sysdeps/x86_64/fpu/multiarch/svml_d_sinf8_core-sse.S: This.
Don't include <sysdep.h> nor <init-arch.h>.
(_ZGVdN8v_sinf): Removed.
|
|
* sysdeps/x86_64/fpu/multiarch/Makefile (libm-sysdep_routines):
Add s_ceil-sse4_1, s_ceilf-sse4_1, s_floor-sse4_1,
s_floorf-sse4_1, s_nearbyint-sse4_1, s_nearbyintf-sse4_1,
s_rint-sse4_1 and s_rintf-sse4_1.
* sysdeps/x86_64/fpu/multiarch/ifunc-sse4_1.h: New file.
* sysdeps/x86_64/fpu/multiarch/s_ceil.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_ceilf.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_floor.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_floorf.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_nearbyint.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_nearbyintf.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_rint.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_rintf.c: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_ceil.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_ceil-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__ceil): Removed.
* sysdeps/x86_64/fpu/multiarch/s_ceilf.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_ceilf-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__ceilf): Removed.
* sysdeps/x86_64/fpu/multiarch/s_floor.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_floor-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__floor): Removed.
* sysdeps/x86_64/fpu/multiarch/s_floorf.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_floorf-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__floorf): Removed.
* sysdeps/x86_64/fpu/multiarch/s_nearbyint.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_nearbyint-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__nearbyint): Removed.
* sysdeps/x86_64/fpu/multiarch/s_nearbyintf.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_nearbyintf-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__nearbyintf): Removed.
* sysdeps/x86_64/fpu/multiarch/s_rint.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_rint-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__rint): Removed.
* sysdeps/x86_64/fpu/multiarch/s_rintf.S: Renamed to ...
* sysdeps/x86_64/fpu/multiarch/s_rintf-sse4_1.S: This. Don't
include <machine/asm.h> nor <init-arch.h>. Include <sysdep.h>.
(__rintf): Removed.
|
|
GCC added support for -mfma4 in version 4.5. Thus the configure tests
for this support are obsolete, and this patch removes them.
Tested for x86_64 and x86 (testsuite, and that installed stripped
shared libraries are unchanged by this patch).
* sysdeps/i386/configure.ac (libc_cv_cc_fma4): Remove configure
test.
* sysdeps/i386/configure: Regenerated.
* sysdeps/x86_64/configure.ac (libc_cv_cc_fma4): Remove configure
test.
* sysdeps/x86_64/configure: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile [$(have-mfma4) = yes]:
Make code unconditional.
* sysdeps/x86_64/fpu/multiarch/e_asin.c [HAVE_FMA4_SUPPORT]:
Likewise.
* sysdeps/x86_64/fpu/multiarch/e_atan2.c [HAVE_FMA4_SUPPORT]:
Likewise.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* sysdeps/x86_64/fpu/multiarch/e_exp.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* sysdeps/x86_64/fpu/multiarch/e_log.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* sysdeps/x86_64/fpu/multiarch/e_pow.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
* sysdeps/x86_64/fpu/multiarch/s_atan.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* sysdeps/x86_64/fpu/multiarch/s_fma.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* sysdeps/x86_64/fpu/multiarch/s_fmaf.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* sysdeps/x86_64/fpu/multiarch/s_sin.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* sysdeps/x86_64/fpu/multiarch/s_tan.c [HAVE_FMA4_SUPPORT]: Make
code unconditional.
[!HAVE_FMA4_SUPPORT]: Remove conditional code.
* config.h.in (HAVE_FMA4_SUPPORT): Remove #undef.
|
|
GCC added support for -mavx and -msse2avx in version 4.4. Thus the
configure tests for this support are obsolete, and this patch removes
them.
Tested for x86_64 and x86 (testsuite, and that installed stripped
shared libraries are unchanged by this patch).
* sysdeps/i386/configure.ac (libc_cv_cc_avx): Remove configure
test.
(libc_cv_cc_sse2avx): Likewise.
* sysdeps/i386/configure: Regenerated.
* sysdeps/i386/i686/multiarch/Makefile
[$(subdir)$(config-cflags-avx) = mathyes]: Change conditional to
[$(subdir) = math].
* sysdeps/i386/i686/multiarch/s_fma-fma.c [HAVE_AVX_SUPPORT]: Make
code unconditional.
* sysdeps/i386/i686/multiarch/s_fma.c [HAVE_AVX_SUPPORT]:
Likewise.
* sysdeps/i386/i686/multiarch/s_fmaf-fma.c [HAVE_AVX_SUPPORT]:
Likewise.
* sysdeps/i386/i686/multiarch/s_fmaf.c [HAVE_AVX_SUPPORT]:
Likewise.
* sysdeps/x86_64/configure.ac (libc_cv_cc_avx): Remove configure
test.
(libc_cv_cc_sse2avx): Likewise.
* sysdeps/x86_64/configure: Regenerated.
* sysdeps/x86_64/Makefile [$(config-cflags-avx) = yes]: Make code
unconditional.
* sysdeps/x86_64/dl-trampoline.h (_dl_runtime_profile)
[HAVE_AVX_SUPPORT || HAVE_AVX512_ASM_SUPPORT]: Make code
unconditional.
(_dl_runtime_profile)
[!(HAVE_AVX_SUPPORT || HAVE_AVX512_ASM_SUPPORT)]: Remove
conditional code.
* sysdeps/x86_64/fpu/multiarch/Makefile
[$(config-cflags-sse2avx) = yes]: Make code unconditional.
* sysdeps/x86_64/fpu/multiarch/e_atan2.c
[HAVE_FMA4_SUPPORT || HAVE_AVX_SUPPORT]: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_exp.c
[HAVE_FMA4_SUPPORT || HAVE_AVX_SUPPORT]: Likewise.
* sysdeps/x86_64/fpu/multiarch/e_log.c
[HAVE_FMA4_SUPPORT || HAVE_AVX_SUPPORT]: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_atan.c
[HAVE_FMA4_SUPPORT || HAVE_AVX_SUPPORT]: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_fma.c [HAVE_AVX_SUPPORT]:
Likewise.
* sysdeps/x86_64/fpu/multiarch/s_fmaf.c [HAVE_AVX_SUPPORT]:
Likewise.
* sysdeps/x86_64/fpu/multiarch/s_sin.c
[HAVE_FMA4_SUPPORT || HAVE_AVX_SUPPORT]: Likewise.
* sysdeps/x86_64/fpu/multiarch/s_tan.c
[HAVE_FMA4_SUPPORT || HAVE_AVX_SUPPORT]: Likewise.
* sysdeps/x86_64/multiarch/strcmp.S [HAVE_AVX_SUPPORT]: Likewise.
* config.h.in (HAVE_AVX_SUPPORT): Remove #undef.
(HAVE_SSE2AVX_SUPPORT): Likewise.
|
|
The x86_64 fma4 version of pow fails to disable contraction of
operations other than those explicitly intended to use fma
instructions, so resulting in large ulps errors on processors with
fma4 instructions, as in bug 18104 (165ulp for the test added for that
bug; error originally reported by "blaaa" on #glibc). This patch adds
$(config-cflags-nofma) for e_pow-fma4.c, corresponding to the use for
e_pow.c in sysdeps/ieee754/dbl-64/Makefile.
Tested for x86_64 on a processor with fma4.
[BZ #19003]
* sysdeps/x86_64/fpu/multiarch/Makefile (CFLAGS-e_pow-fma4.c): Add
$(config-cflags-nofma).
|
|
Here is implementation of vectorized sincosf containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* NEWS: Mention addition of x86_64 vector sincosf.
* math/test-float-vlen16.h: Added wrapper for sincosf tests.
* math/test-float-vlen4.h: Likewise.
* math/test-float-vlen8.h: Likewise.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added.
* sysdeps/x86/fpu/bits/math-vector.h: Added sincosf SIMD declaration.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines):
Added build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core_sse4.S
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core_avx2.S
* sysdeps/x86_64/fpu/svml_s_sincosf16_core.S
* sysdeps/x86_64/fpu/svml_s_sincosf4_core.S
* sysdeps/x86_64/fpu/svml_s_sincosf8_core.S
* sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S
* sysdeps/x86_64/fpu/svml_s_sincosf_data.S: New file.
* sysdeps/x86_64/fpu/svml_s_sincosf_data.h: New file.
* sysdeps/x86_64/fpu/svml_s_wrapper_impl.h: Added 3 argument wrappers.
* sysdeps/x86_64/fpu/test-float-vlen16.c: : Vector sincosf tests.
* sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8.c: Likewise.
|
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Here is implementation of vectorized sincos containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* NEWS: Mention addition of x86_64 vector sincos.
* bits/libm-simd-decl-stubs.h: Added stubs for sincos.
* math/math.h (__MATHDECL_VEC): New macro.
* math/bits/mathcalls.h: Added sincos declaration with __MATHDECL_VEC.
* math/gen-libm-have-vector-test.sh: Added generation of sincos wrapper
declaration under condition.
* math/test-vec-loop.h (TEST_VEC_LOOP): Refactored.
* math/test-double-vlen2.h: Added wrapper for sincos tests, reflected
TEST_VEC_LOOP change.
* math/test-double-vlen4.h: Likewise.
* math/test-double-vlen8.h: Likewise.
* math/test-float-vlen16.h: Reflected TEST_VEC_LOOP change.
* math/test-float-vlen4.h: Likewise.
* math/test-float-vlen8.h: Likewise.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added.
* sysdeps/x86/fpu/bits/math-vector.h: Added sincos SIMD declaration.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines):
Added build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_sincos2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_sincos4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_sincos8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_sincos_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_sincos_data.h: New file.
* sysdeps/x86_64/fpu/svml_d_wrapper_impl.h: Added wrappers for sincos.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Vector sincos tests.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
|
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Here is implementation of vectorized powf containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for powf.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines):
Added build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/svml_s_wrapper_impl.h: Added 2 argument wrappers.
* sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core_avx2.S: New file.
* sysdeps/x86_64/fpu/svml_s_powf16_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_powf4_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_powf8_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_s_powf_data.S: New file.
* sysdeps/x86_64/fpu/svml_s_powf_data.h: New file.
* sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Vector powf tests.
* sysdeps/x86_64/fpu/test-float-vlen16.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8.c: Likewise.
* math/test-float-vlen16.h: Fixed 2 argument macro.
* math/test-float-vlen4.h: Likewise.
* math/test-float-vlen8.h: Likewise.
* NEWS: Mention addition of x86_64 vector powf.
|
|
Here is implementation of vectorized pow containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* bits/libm-simd-decl-stubs.h: Added stubs for pow.
* math/bits/mathcalls.h: Added pow declaration with __MATHCALL_VEC.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for pow.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/svml_d_wrapper_impl.h: Added 2 argument wrappers.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow_data.h: New file.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector pow test.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector pow.
|
|
Here is implementation of vectorized expf containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for expf.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core_avx2.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf16_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf4_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf8_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf_data.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf_data.h: New file.
* sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Vector expf tests.
* sysdeps/x86_64/fpu/test-float-vlen16.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector expf.
|
|
Here is implementation of vectorized exp containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* bits/libm-simd-decl-stubs.h: Added stubs for exp.
* math/bits/mathcalls.h: Added exp declaration with __MATHCALL_VEC.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for exp.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_exp_data.h: New file.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector exp test.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector exp.
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Here is implementation of vectorized logf containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for logf.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core_avx2.S: New file.
* sysdeps/x86_64/fpu/svml_s_logf16_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_logf4_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_logf8_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_s_logf_data.S: New file.
* sysdeps/x86_64/fpu/svml_s_logf_data.h: New file.
* sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Vector logf tests.
* sysdeps/x86_64/fpu/test-float-vlen16.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector logf.
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Here is implementation of vectorized log containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* bits/libm-simd-decl-stubs.h: Added stubs for log.
* math/bits/mathcalls.h: Added log declaration with __MATHCALL_VEC.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for log.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_log2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_log4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_log2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_log4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_log4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_log8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_log_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_log_data.h: New file.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector log test.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector log.
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Here is implementation of vectorized sinf containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration for sinf.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core_avx2.S: New file.
* sysdeps/x86_64/fpu/svml_s_sinf16_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_sinf4_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_sinf8_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_s_sinf_data.S: New file.
* sysdeps/x86_64/fpu/svml_s_sinf_data.h: New file.
* sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Vector sinf tests.
* sysdeps/x86_64/fpu/test-float-vlen16.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector sinf.
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Here is implementation of vectorized sin containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* bits/libm-simd-decl-stubs.h: Added stubs for sin.
* math/bits/mathcalls.h: Added sin declaration with __MATHCALL_VEC.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: SIMD declaration for sin.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_sin2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_sin4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_sin8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_sin_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_sin_data.h: New file.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector sin test.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector sin.
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Here is implementation of vectorized cosf containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/svml_s_cosf4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core_sse4.S: New file.
* sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_s_cosf8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core_avx2.S: New file.
* sysdeps/x86_64/fpu/svml_s_cosf16_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_s_wrapper_impl.h: New file.
* sysdeps/x86_64/fpu/svml_s_cosf_data.S: New file.
* sysdeps/x86_64/fpu/svml_s_cosf_data.h: New file.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration for cosf.
* NEWS: Mention addition of x86_64 vector cosf.
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Here is implementation of cos containing SSE, AVX, AVX2 and AVX512
versions according to Vector ABI which had been discussed in
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
Vector math library build and ABI testing enabled by default for x86_64.
* sysdeps/x86_64/fpu/Makefile: New file.
* sysdeps/x86_64/fpu/Versions: New file.
* sysdeps/x86_64/fpu/svml_d_cos_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_cos_data.h: New file.
* sysdeps/x86_64/fpu/svml_d_cos2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_cos4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_cos8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_wrapper_impl.h: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration for cos.
* math/bits/mathcalls.h: Added cos declaration with __MATHCALL_VEC.
* sysdeps/x86_64/configure.ac: Options for libmvec build.
* sysdeps/x86_64/configure: Regenerated.
* sysdeps/x86_64/sysdep.h (cfi_offset_rel_rsp): New macro.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New file.
* manual/install.texi (Configuring and compiling): Document
--disable-mathvec.
* INSTALL: Regenerated.
* NEWS: Mention addition of libmvec and x86_64 vector cos.
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Some of the AVX-specific code is not giving enough speed-up to
justify the extra code.
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