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path: root/sysdeps/x86/cpu-features.h
AgeCommit message (Expand)AuthorFilesLines
2020-09-11x86: Install <sys/platform/x86.h> [BZ #26124]H.J. Lu1-857/+0
2020-08-05x86: Rename Intel CPU feature namesH.J. Lu1-9/+9
2020-07-13x86: Support usable check for all CPU featuresH.J. Lu1-138/+120
2020-07-06x86: Add thresholds for "rep movsb/stosb" to tunablesH.J. Lu1-0/+4
2020-07-06x86: Detect Extended Feature Disable (XFD)H.J. Lu1-0/+3
2020-07-06x86: Correct bit_cpu_CLFSH [BZ #26208]H.J. Lu1-1/+1
2020-06-26x86: Detect Intel Advanced Matrix ExtensionsH.J. Lu1-0/+20
2020-06-22x86: Update CPU feature detection [BZ #26149]H.J. Lu1-261/+158
2020-06-18x86: Update F16C detection [BZ #26133]H.J. Lu1-3/+3
2020-06-17x86: Correct bit_cpu_CLFLUSHOPT [BZ #26128]H.J. Lu1-1/+1
2020-04-30x86: Add CPU Vendor ID detection support for Zhaoxin processorsmayshao1-0/+1
2020-01-01Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2019-09-07Prefer https to http for gnu.org and fsf.org URLsPaul Eggert1-1/+1
2019-01-01Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2018-12-03x86: Extend CPUID support in struct cpu_featuresH.J. Lu1-194/+869
2018-09-20Invert sense of list of i686-class processors in sysdeps/x86/cpu-features.h.Joseph Myers1-18/+7
2018-08-06x86: Move STATE_SAVE_OFFSET/STATE_SAVE_MASK to sysdep.hH.J. Lu1-14/+0
2018-08-02Rename the glibc.tune namespace to glibc.cpuSiddhesh Poyarekar1-1/+1
2018-07-26x86: Populate COMMON_CPUID_INDEX_80000001 for Intel CPUs [BZ #23459]H.J. Lu1-1/+1
2018-07-26x86: Correct index_cpu_LZCNT [BZ # 23456]H.J. Lu1-1/+1
2018-05-21x86-64: Check Prefer_FSRM in ifunc-memmove.hH.J. Lu1-0/+2
2018-05-21Initial Fast Short REP MOVSB (FSRM) supportH.J. Lu1-0/+3
2018-01-01Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2017-10-20x86-64: Use fxsave/xsave/xsavec in _dl_runtime_resolve [BZ #21265]H.J. Lu1-7/+27
2017-09-12x86: Add MathVec_Prefer_No_AVX512 to cpu-features [BZ #21967]H.J. Lu1-0/+2
2017-08-25x86: Remove assembly versions of index_cpu_*/index_arch_*H.J. Lu1-42/+1
2017-08-14x86: Add IBT/SHSTK bits to cpu-featuresH.J. Lu1-0/+8
2017-08-04x86: Remove assembly versions of HAS_CPU_FEATURE/HAS_ARCH_FEATUREH.J. Lu1-57/+0
2017-06-21x86: Rename glibc.tune.ifunc to glibc.tune.hwcapsH.J. Lu1-3/+3
2017-06-20tunables: Add IFUNC selection and cache sizesH.J. Lu1-0/+8
2017-06-05x86-64: Optimize memcmp/wmemcmp with AVX2 and MOVBEH.J. Lu1-0/+1
2017-05-03x86: Set dl_platform and dl_hwcap from CPU features [BZ #21391]H.J. Lu1-0/+15
2017-04-18x86: Use AVX2 memcpy/memset on Skylake server [BZ #21396]H.J. Lu1-0/+3
2017-04-18x86: Set Prefer_No_VZEROUPPER if AVX512ER is availableH.J. Lu1-0/+15
2017-04-07Check if SSE is available with HAS_CPU_FEATUREH.J. Lu1-0/+4
2017-01-01Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2016-09-06X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]H.J. Lu1-0/+6
2016-08-19X86: Change bit_YMM_state to (1 << 2)H.J. Lu1-1/+1
2016-06-30Check Prefer_ERMS in memmove/memcpy/mempcpy/memsetH.J. Lu1-0/+3
2016-05-19Check the HTT bit before counting logical threadsH.J. Lu1-0/+3
2016-05-11Remove x86 ifunc-defines.sym and rtld-global-offsets.symH.J. Lu1-2/+1
2016-03-28Initial Enhanced REP MOVSB/STOSB (ERMS) supportH.J. Lu1-0/+4
2016-03-28[x86] Add a feature bit: Fast_Unaligned_CopyH.J. Lu1-0/+3
2016-03-22Set index_arch_AVX_Fast_Unaligned_Load only for Intel processorsH.J. Lu1-2/+8
2016-03-10Add _arch_/_cpu_ to index_*/bit_* in x86 cpu-features.hH.J. Lu1-109/+113
2016-01-04Update copyright dates with scripts/update-copyrights.Joseph Myers1-1/+1
2015-12-19Added memset optimized with AVX512 for KNL hardware.Andrew Senkevich1-0/+4
2015-12-15Add Prefer_MAP_32BIT_EXEC to map executable pages with MAP_32BIThjl/32bit/masterH.J. Lu1-0/+3
2015-08-27Detect and select i586/i686 implementation at run-timefedora/masterH.J. Lu1-3/+17
2015-08-19Also check __i586__/__i686__ for HAS_I586/HAS_I686H.J. Lu1-8/+9
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