1 files changed, 13 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index d976999..07a4bbb 100644
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -35,5 +35,18 @@ feenableexcept (int excepts)
 
   _FPU_SETCW (fpcr);
 
+  /* Trapping exceptions are optional in AArch64 the relevant enable
+     bits in FPCR are RES0 hence the absence of support can be
+     detected by reading back the FPCR and comparing with the required
+     value.  */
+  if (excepts)
+    {
+      fpu_control_t updated_fpcr;
+
+      _FPU_GETCW (updated_fpcr);
+      if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
+	return -1;
+    }
+
   return original_excepts;
 }