diff options
| -rw-r--r-- | ChangeLog | 5 | ||||
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 6 |
2 files changed, 9 insertions, 2 deletions
@@ -1,3 +1,8 @@ +2017-06-02 H.J. Lu <hongjiu.lu@intel.com> + + * sysdeps/x86/cacheinfo.c (__x86_shared_non_temporal_threshold): + Set to the 3/4 of the total shared cache size. + 2017-06-02 Rical Jasan <ricaljasan@pacific.net> * manual/errno.texi: Remove redundant error strings. diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 12ffeef..f66f2b8 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -767,8 +767,10 @@ intel_bug_no_cache_info: /* The large memcpy micro benchmark in glibc shows that 6 times of shared cache size is the approximate value above which non-temporal - store becomes faster. */ - __x86_shared_non_temporal_threshold = __x86_shared_cache_size * 6; + store becomes faster on a 8-core processor. This is the 3/4 of the + total shared cache size. */ + __x86_shared_non_temporal_threshold + = __x86_shared_cache_size * threads * 3 / 4; } #endif |