diff options
| -rw-r--r-- | ChangeLog | 5 | ||||
| -rw-r--r-- | sysdeps/mips/memcpy.S | 2 | ||||
| -rw-r--r-- | sysdeps/mips/memset.S | 2 | ||||
| -rw-r--r-- | sysdeps/mips/strcmp.S | 2 |
4 files changed, 8 insertions, 3 deletions
@@ -1,5 +1,10 @@ 2015-02-16 Joseph Myers <joseph@codesourcery.com> + * sysdeps/mips/memcpy.S [_COMPILING_NEWLIB]: Change condition to + [defined _COMPILING_NEWLIB]. + * sysdeps/mips/memset.S [_COMPILING_NEWLIB]: Likewise. + * sysdeps/mips/strcmp.S [_COMPILING_NEWLIB]: Likewise. + * sysdeps/mips/sys/asm.h [__mips_isa_rev < 6]: Change condition to [!defined __mips_isa_rev || __mips_isa_rev < 6]. diff --git a/sysdeps/mips/memcpy.S b/sysdeps/mips/memcpy.S index 715abcf..a9ac059 100644 --- a/sysdeps/mips/memcpy.S +++ b/sysdeps/mips/memcpy.S @@ -27,7 +27,7 @@ # include <sys/asm.h> # define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED # define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#elif _COMPILING_NEWLIB +#elif defined _COMPILING_NEWLIB # include "machine/asm.h" # include "machine/regdef.h" # define PREFETCH_LOAD_HINT PREFETCH_HINT_LOAD_STREAMED diff --git a/sysdeps/mips/memset.S b/sysdeps/mips/memset.S index 940a225..cf16b26 100644 --- a/sysdeps/mips/memset.S +++ b/sysdeps/mips/memset.S @@ -24,7 +24,7 @@ # include <regdef.h> # include <sys/asm.h> # define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE -#elif _COMPILING_NEWLIB +#elif defined _COMPILING_NEWLIB # include "machine/asm.h" # include "machine/regdef.h" # define PREFETCH_STORE_HINT PREFETCH_HINT_PREPAREFORSTORE diff --git a/sysdeps/mips/strcmp.S b/sysdeps/mips/strcmp.S index 66fe06c..7ba79e7 100644 --- a/sysdeps/mips/strcmp.S +++ b/sysdeps/mips/strcmp.S @@ -22,7 +22,7 @@ # include <sysdep.h> # include <regdef.h> # include <sys/asm.h> -#elif _COMPILING_NEWLIB +#elif defined _COMPILING_NEWLIB # include "machine/asm.h" # include "machine/regdef.h" #else |