diff options
-rw-r--r-- | ChangeLog | 18 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/e_sqrt.c | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/e_sqrtf.c | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fclrexcpt.c | 4 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fedisblxcpt.c | 10 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/feenablxcpt.c | 10 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fegetexcept.c | 10 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/feholdexcpt.c | 5 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fenv_libc.h | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fesetenv.c | 4 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/feupdateenv.c | 6 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fgetexcptflg.c | 2 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fraiseexcpt.c | 12 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/fsetexcptflg.c | 8 | ||||
-rw-r--r-- | sysdeps/powerpc/fpu/ftestexcept.c | 2 |
15 files changed, 57 insertions, 40 deletions
@@ -1,5 +1,23 @@ 2013-10-04 Anton Blanchard <anton@au1.ibm.com> + * sysdeps/powerpc/fpu/fenv_libc.h (fenv_union_t): Replace int + array with long long. + * sysdeps/powerpc/fpu/e_sqrt.c (__slow_ieee754_sqrt): Adjust. + * sysdeps/powerpc/fpu/e_sqrtf.c (__slow_ieee754_sqrtf): Adjust. + * sysdeps/powerpc/fpu/fclrexcpt.c (__feclearexcept): Adjust. + * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Adjust. + * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Adjust. + * sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Adjust. + * sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Adjust. + * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Adjust. + * sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Adjust. + * sysdeps/powerpc/fpu/fgetexcptflg.c (__fegetexceptflag): Adjust. + * sysdeps/powerpc/fpu/fraiseexcpt.c (__feraiseexcept): Adjust. + * sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Adjust. + * sysdeps/powerpc/fpu/ftestexcept.c (fetestexcept): Adjust. + +2013-10-04 Anton Blanchard <anton@au1.ibm.com> + * sysdeps/powerpc/bits/mathinline.h (__signbitf): Use builtin. (__signbit): Likewise. Correct for little-endian. (__signbitl): Call __signbit. diff --git a/sysdeps/powerpc/fpu/e_sqrt.c b/sysdeps/powerpc/fpu/e_sqrt.c index 3efe277..2d50fb5 100644 --- a/sysdeps/powerpc/fpu/e_sqrt.c +++ b/sysdeps/powerpc/fpu/e_sqrt.c @@ -145,7 +145,7 @@ __slow_ieee754_sqrt (double x) feraiseexcept (FE_INVALID_SQRT); fenv_union_t u = { .fenv = fegetenv_register () }; - if ((u.l[1] & FE_INVALID) == 0) + if ((u.l & FE_INVALID) == 0) #endif feraiseexcept (FE_INVALID); x = a_nan.value; diff --git a/sysdeps/powerpc/fpu/e_sqrtf.c b/sysdeps/powerpc/fpu/e_sqrtf.c index 6e50a3c..91d2d37 100644 --- a/sysdeps/powerpc/fpu/e_sqrtf.c +++ b/sysdeps/powerpc/fpu/e_sqrtf.c @@ -121,7 +121,7 @@ __slow_ieee754_sqrtf (float x) feraiseexcept (FE_INVALID_SQRT); fenv_union_t u = { .fenv = fegetenv_register () }; - if ((u.l[1] & FE_INVALID) == 0) + if ((u.l & FE_INVALID) == 0) #endif feraiseexcept (FE_INVALID); x = a_nan.value; diff --git a/sysdeps/powerpc/fpu/fclrexcpt.c b/sysdeps/powerpc/fpu/fclrexcpt.c index 86575db..7f66e21 100644 --- a/sysdeps/powerpc/fpu/fclrexcpt.c +++ b/sysdeps/powerpc/fpu/fclrexcpt.c @@ -28,8 +28,8 @@ __feclearexcept (int excepts) u.fenv = fegetenv_register (); /* Clear the relevant bits. */ - u.l[1] = u.l[1] & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID) - | (excepts & FPSCR_STICKY_BITS)); + u.l = u.l & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID) + | (excepts & FPSCR_STICKY_BITS)); /* Put the new state in effect. */ fesetenv_register (u.fenv); diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c index 659566b..f2c45a6 100644 --- a/sysdeps/powerpc/fpu/fedisblxcpt.c +++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -32,15 +32,15 @@ fedisableexcept (int excepts) fe.fenv = fegetenv_register (); if (excepts & FE_INEXACT) - fe.l[1] &= ~(1 << (31 - FPSCR_XE)); + fe.l &= ~(1 << (31 - FPSCR_XE)); if (excepts & FE_DIVBYZERO) - fe.l[1] &= ~(1 << (31 - FPSCR_ZE)); + fe.l &= ~(1 << (31 - FPSCR_ZE)); if (excepts & FE_UNDERFLOW) - fe.l[1] &= ~(1 << (31 - FPSCR_UE)); + fe.l &= ~(1 << (31 - FPSCR_UE)); if (excepts & FE_OVERFLOW) - fe.l[1] &= ~(1 << (31 - FPSCR_OE)); + fe.l &= ~(1 << (31 - FPSCR_OE)); if (excepts & FE_INVALID) - fe.l[1] &= ~(1 << (31 - FPSCR_VE)); + fe.l &= ~(1 << (31 - FPSCR_VE)); fesetenv_register (fe.fenv); new = __fegetexcept (); diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index fc4bfff..472796d 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -32,15 +32,15 @@ feenableexcept (int excepts) fe.fenv = fegetenv_register (); if (excepts & FE_INEXACT) - fe.l[1] |= (1 << (31 - FPSCR_XE)); + fe.l |= (1 << (31 - FPSCR_XE)); if (excepts & FE_DIVBYZERO) - fe.l[1] |= (1 << (31 - FPSCR_ZE)); + fe.l |= (1 << (31 - FPSCR_ZE)); if (excepts & FE_UNDERFLOW) - fe.l[1] |= (1 << (31 - FPSCR_UE)); + fe.l |= (1 << (31 - FPSCR_UE)); if (excepts & FE_OVERFLOW) - fe.l[1] |= (1 << (31 - FPSCR_OE)); + fe.l |= (1 << (31 - FPSCR_OE)); if (excepts & FE_INVALID) - fe.l[1] |= (1 << (31 - FPSCR_VE)); + fe.l |= (1 << (31 - FPSCR_VE)); fesetenv_register (fe.fenv); new = __fegetexcept (); diff --git a/sysdeps/powerpc/fpu/fegetexcept.c b/sysdeps/powerpc/fpu/fegetexcept.c index f3d5724..23d47a2 100644 --- a/sysdeps/powerpc/fpu/fegetexcept.c +++ b/sysdeps/powerpc/fpu/fegetexcept.c @@ -27,15 +27,15 @@ __fegetexcept (void) fe.fenv = fegetenv_register (); - if (fe.l[1] & (1 << (31 - FPSCR_XE))) + if (fe.l & (1 << (31 - FPSCR_XE))) result |= FE_INEXACT; - if (fe.l[1] & (1 << (31 - FPSCR_ZE))) + if (fe.l & (1 << (31 - FPSCR_ZE))) result |= FE_DIVBYZERO; - if (fe.l[1] & (1 << (31 - FPSCR_UE))) + if (fe.l & (1 << (31 - FPSCR_UE))) result |= FE_UNDERFLOW; - if (fe.l[1] & (1 << (31 - FPSCR_OE))) + if (fe.l & (1 << (31 - FPSCR_OE))) result |= FE_OVERFLOW; - if (fe.l[1] & (1 << (31 - FPSCR_VE))) + if (fe.l & (1 << (31 - FPSCR_VE))) result |= FE_INVALID; return result; diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c index 013d2bf..0ecf0f7 100644 --- a/sysdeps/powerpc/fpu/feholdexcpt.c +++ b/sysdeps/powerpc/fpu/feholdexcpt.c @@ -30,13 +30,12 @@ feholdexcept (fenv_t *envp) /* Clear everything except for the rounding modes and non-IEEE arithmetic flag. */ - new.l[1] = old.l[1] & 7; - new.l[0] = old.l[0]; + new.l = old.l & 0xffffffff00000007LL; /* If the old env had any enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ - if ((old.l[1] & _FPU_MASK_ALL) != 0) + if ((old.l & _FPU_MASK_ALL) != 0) (void)__fe_mask_env (); /* Put the new state in effect. */ diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 1910951..baa2a7d 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -69,7 +69,7 @@ libm_hidden_proto (__fe_nomask_env) typedef union { fenv_t fenv; - unsigned int l[2]; + unsigned long long l; } fenv_union_t; diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index e92adb4..6c00b26 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -34,14 +34,14 @@ __fesetenv (const fenv_t *envp) exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ - if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) + if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ - if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) + if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); fesetenv_register (*envp); diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c index 6500ea1..6775044 100644 --- a/sysdeps/powerpc/fpu/feupdateenv.c +++ b/sysdeps/powerpc/fpu/feupdateenv.c @@ -34,20 +34,20 @@ __feupdateenv (const fenv_t *envp) /* Restore rounding mode and exception enable from *envp and merge exceptions. Leave fraction rounded/inexact and FP result/CC bits unchanged. */ - new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF); + new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff); /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ - if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) + if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ - if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) + if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ diff --git a/sysdeps/powerpc/fpu/fgetexcptflg.c b/sysdeps/powerpc/fpu/fgetexcptflg.c index f6327ce..1395bed 100644 --- a/sysdeps/powerpc/fpu/fgetexcptflg.c +++ b/sysdeps/powerpc/fpu/fgetexcptflg.c @@ -27,7 +27,7 @@ __fegetexceptflag (fexcept_t *flagp, int excepts) u.fenv = fegetenv_register (); /* Return (all of) it. */ - *flagp = u.l[1] & excepts & FE_ALL_EXCEPT; + *flagp = u.l & excepts & FE_ALL_EXCEPT; /* Success. */ return 0; diff --git a/sysdeps/powerpc/fpu/fraiseexcpt.c b/sysdeps/powerpc/fpu/fraiseexcpt.c index 9118c19..6193071 100644 --- a/sysdeps/powerpc/fpu/fraiseexcpt.c +++ b/sysdeps/powerpc/fpu/fraiseexcpt.c @@ -33,11 +33,11 @@ __feraiseexcept (int excepts) u.fenv = fegetenv_register (); /* Add the exceptions */ - u.l[1] = (u.l[1] - | (excepts & FPSCR_STICKY_BITS) - /* Turn FE_INVALID into FE_INVALID_SOFTWARE. */ - | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT)) - & FE_INVALID_SOFTWARE)); + u.l = (u.l + | (excepts & FPSCR_STICKY_BITS) + /* Turn FE_INVALID into FE_INVALID_SOFTWARE. */ + | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT)) + & FE_INVALID_SOFTWARE)); /* Store the new status word (along with the rest of the environment), triggering any appropriate exceptions. */ @@ -49,7 +49,7 @@ __feraiseexcept (int excepts) don't have FE_INVALID_SOFTWARE implemented. Detect this case and raise FE_INVALID_SNAN instead. */ u.fenv = fegetenv_register (); - if ((u.l[1] & FE_INVALID) == 0) + if ((u.l & FE_INVALID) == 0) set_fpscr_bit (FPSCR_VXSNAN); } diff --git a/sysdeps/powerpc/fpu/fsetexcptflg.c b/sysdeps/powerpc/fpu/fsetexcptflg.c index c050d40..0d309c8 100644 --- a/sysdeps/powerpc/fpu/fsetexcptflg.c +++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -31,10 +31,10 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts) flag = *flagp & excepts; /* Replace the exception status */ - u.l[1] = ((u.l[1] & ~(FPSCR_STICKY_BITS & excepts)) - | (flag & FPSCR_STICKY_BITS) - | (flag >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT)) - & FE_INVALID_SOFTWARE)); + u.l = ((u.l & ~(FPSCR_STICKY_BITS & excepts)) + | (flag & FPSCR_STICKY_BITS) + | (flag >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT)) + & FE_INVALID_SOFTWARE)); /* Store the new status word (along with the rest of the environment). This may cause floating-point exceptions if the restored state diff --git a/sysdeps/powerpc/fpu/ftestexcept.c b/sysdeps/powerpc/fpu/ftestexcept.c index 0dbc3be..86eea0f 100644 --- a/sysdeps/powerpc/fpu/ftestexcept.c +++ b/sysdeps/powerpc/fpu/ftestexcept.c @@ -28,6 +28,6 @@ fetestexcept (int excepts) /* The FE_INVALID bit is dealt with correctly by the hardware, so we can just: */ - return u.l[1] & excepts; + return u.l & excepts; } libm_hidden_def (fetestexcept) |