diff options
40 files changed, 174 insertions, 228 deletions
@@ -1,5 +1,53 @@ 2015-08-13 H.J. Lu <hongjiu.lu@intel.com> + * math/Makefile ($(addprefix $(objpfx), $(libm-vec-tests))): + Remove $(objpfx)init-arch.o. + * sysdeps/x86_64/fpu/Makefile (libmvec-support): Remove + init-arch. + * sysdeps/x86_64/fpu/math-tests-arch.h (avx_usable): Removed. + (INIT_ARCH_EXT): Defined as empty. + (CHECK_ARCH_EXT): Replace HAS_XXX with HAS_ARCH_FEATURE (XXX). + * sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S: Remove + __init_cpu_features call. Replace HAS_XXX with + HAS_CPU_FEATURE/HAS_ARCH_FEATURE (XXX). + * sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S: Likewise. + * sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S: Likewise. + +2015-08-13 H.J. Lu <hongjiu.lu@intel.com> + * sysdeps/i386/i686/fpu/multiarch/e_expf.c: Replace HAS_XXX with HAS_CPU_FEATURE/HAS_ARCH_FEATURE (XXX). * sysdeps/i386/i686/fpu/multiarch/s_cosf.c: Likewise. diff --git a/math/Makefile b/math/Makefile index 6388bae..d3b483d 100644 --- a/math/Makefile +++ b/math/Makefile @@ -263,7 +263,7 @@ $(objpfx)libieee.a: $(objpfx)ieee-math.o $(addprefix $(objpfx),$(filter-out $(tests-static) $(libm-vec-tests),$(tests))): $(libm) $(addprefix $(objpfx),$(tests-static)): $(objpfx)libm.a $(addprefix $(objpfx), $(libm-vec-tests)): $(objpfx)%: $(libm) $(libmvec) \ - $(objpfx)init-arch.o $(objpfx)%-wrappers.o + $(objpfx)%-wrappers.o gmp-objs = $(patsubst %,$(common-objpfx)stdlib/%.o,\ add_n sub_n cmp addmul_1 mul_1 mul_n divmod_1 \ diff --git a/sysdeps/x86_64/fpu/Makefile b/sysdeps/x86_64/fpu/Makefile index 1ebe511..f98f6cf 100644 --- a/sysdeps/x86_64/fpu/Makefile +++ b/sysdeps/x86_64/fpu/Makefile @@ -20,7 +20,7 @@ libmvec-support += svml_d_cos2_core svml_d_cos4_core_avx \ svml_d_pow_data svml_s_powf4_core svml_s_powf8_core_avx \ svml_s_powf8_core svml_s_powf16_core svml_s_powf_data \ svml_s_sincosf4_core svml_s_sincosf8_core_avx \ - svml_s_sincosf8_core svml_s_sincosf16_core init-arch + svml_s_sincosf8_core svml_s_sincosf16_core endif # Variables for libmvec tests. diff --git a/sysdeps/x86_64/fpu/math-tests-arch.h b/sysdeps/x86_64/fpu/math-tests-arch.h index e8833bf..fb8251b 100644 --- a/sysdeps/x86_64/fpu/math-tests-arch.h +++ b/sysdeps/x86_64/fpu/math-tests-arch.h @@ -19,66 +19,36 @@ #if defined REQUIRE_AVX # include <init-arch.h> -/* Set to 1 if AVX supported. */ -static int avx_usable; - -# define INIT_ARCH_EXT \ - do \ - { \ - __init_cpu_features (); \ - avx_usable = __cpu_features.feature[index_AVX_Usable] \ - & bit_AVX_Usable; \ - } \ - while (0) +# define INIT_ARCH_EXT # define CHECK_ARCH_EXT \ do \ { \ - if (!avx_usable) return; \ + if (!HAS_ARCH_FEATURE (AVX_Usable)) return; \ } \ while (0) #elif defined REQUIRE_AVX2 # include <init-arch.h> - /* Set to 1 if AVX2 supported. */ - static int avx2_usable; - -# define INIT_ARCH_EXT \ - do \ - { \ - __init_cpu_features (); \ - avx2_usable = __cpu_features.feature[index_AVX2_Usable] \ - & bit_AVX2_Usable; \ - } \ - while (0) +# define INIT_ARCH_EXT # define CHECK_ARCH_EXT \ do \ { \ - if (!avx2_usable) return; \ + if (!HAS_ARCH_FEATURE (AVX2_Usable)) return; \ } \ while (0) #elif defined REQUIRE_AVX512F # include <init-arch.h> - /* Set to 1 if supported. */ - static int avx512f_usable; - -# define INIT_ARCH_EXT \ - do \ - { \ - __init_cpu_features (); \ - avx512f_usable = __cpu_features.feature[index_AVX512F_Usable] \ - & bit_AVX512F_Usable; \ - } \ - while (0) +# define INIT_ARCH_EXT # define CHECK_ARCH_EXT \ do \ { \ - if (!avx512f_usable) return; \ + if (!HAS_ARCH_FEATURE (AVX512F_Usable)) return; \ } \ while (0) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S index 5f67d83..c64485e 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN2v_cos) .type _ZGVbN2v_cos, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN2v_cos_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_cos_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN2v_cos_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S index 5babb83..6460690 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN4v_cos) .type _ZGVdN4v_cos, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN4v_cos_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_cos_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN4v_cos_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S index d0f4f27..add99a1 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN8v_cos) .type _ZGVeN8v_cos, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features + LOAD_RTLD_GLOBAL_RO_RDX 1: leaq _ZGVeN8v_cos_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN8v_cos_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN8v_cos_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S index ef3dc49..538e991 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN2v_exp) .type _ZGVbN2v_exp, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN2v_exp_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_exp_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN2v_exp_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S index 7f2ebde..c68ca93 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN4v_exp) .type _ZGVdN4v_exp, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN4v_exp_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_exp_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN4v_exp_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S index 7b7c07d..d3985dc 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN8v_exp) .type _ZGVeN8v_exp, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN8v_exp_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8v_exp_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN8v_exp_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN8v_exp_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S index 38d369f..adcb34e 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN2v_log) .type _ZGVbN2v_log, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN2v_log_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_log_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN2v_log_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S index ddb6105..9c9f84a 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN4v_log) .type _ZGVdN4v_log, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN4v_log_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_log_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN4v_log_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S index 76375fd..0ceb9eb 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN8v_log) .type _ZGVeN8v_log, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN8v_log_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8v_log_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN8v_log_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN8v_log_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S index f111388..0fbdb43 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN2vv_pow) .type _ZGVbN2vv_pow, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN2vv_pow_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2vv_pow_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN2vv_pow_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S index 21e3070..0cf5c9b 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN4vv_pow) .type _ZGVdN4vv_pow, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN4vv_pow_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4vv_pow_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN4vv_pow_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S index c1e5e76..9afdf67 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN8vv_pow) .type _ZGVeN8vv_pow, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN8vv_pow_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8vv_pow_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN8vv_pow_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN8vv_pow_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S index 29bd0a7..eec486b 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN2v_sin) .type _ZGVbN2v_sin, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN2v_sin_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2v_sin_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN2v_sin_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S index c3a453a..17cb5c1 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN4v_sin) .type _ZGVdN4v_sin, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN4v_sin_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4v_sin_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN4v_sin_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S index 131f2f4..61ee0c0 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN8v_sin) .type _ZGVeN8v_sin, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN8v_sin_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8v_sin_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN8v_sin_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN8v_sin_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S index e8e5771..3d03c53 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN2vvv_sincos) .type _ZGVbN2vvv_sincos, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN2vvv_sincos_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN2vvv_sincos_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN2vvv_sincos_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S index 64744ff..1cc2b69 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN4vvv_sincos) .type _ZGVdN4vvv_sincos, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN4vvv_sincos_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN4vvv_sincos_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN4vvv_sincos_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S index e331090..850f221 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN8vvv_sincos) .type _ZGVeN8vvv_sincos, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN8vvv_sincos_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN8vvv_sincos_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN8vvv_sincos_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN8vvv_sincos_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S index 0654d3c..227f46e 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN16v_cosf) .type _ZGVeN16v_cosf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN16v_cosf_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_cosf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN16v_cosf_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN16v_cosf_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S index fa2363b..2e98938 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN4v_cosf) .type _ZGVbN4v_cosf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN4v_cosf_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_cosf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN4v_cosf_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S index e14bba4..830b10f 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN8v_cosf) .type _ZGVdN8v_cosf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN8v_cosf_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8v_cosf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN8v_cosf_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S index 62858eb..79ac304 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN16v_expf) .type _ZGVeN16v_expf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN16v_expf_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_expf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN16v_expf_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN16v_expf_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S index 37d38bc..e9781f3 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN4v_expf) .type _ZGVbN4v_expf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN4v_expf_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_expf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN4v_expf_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S index e3dc1b1..41e59ef 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN8v_expf) .type _ZGVdN8v_expf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN8v_expf_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8v_expf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN8v_expf_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S index 68c57e4..fa01161 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN16v_logf) .type _ZGVeN16v_logf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN16v_logf_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_logf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN16v_logf_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN16v_logf_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S index 153ed8e..0f1ca73 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN4v_logf) .type _ZGVbN4v_logf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN4v_logf_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_logf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN4v_logf_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S index 6f50bf6..65d1f7f 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN8v_logf) .type _ZGVdN8v_logf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN8v_logf_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8v_logf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN8v_logf_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S index 3aa9f95..e33e83e 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN16vv_powf) .type _ZGVeN16vv_powf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN16vv_powf_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16vv_powf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN16vv_powf_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN16vv_powf_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S index f88b9ca..28abeec 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN4vv_powf) .type _ZGVbN4vv_powf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN4vv_powf_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4vv_powf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN4vv_powf_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S index 4552e57..0cbbe5d 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN8vv_powf) .type _ZGVdN8vv_powf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN8vv_powf_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8vv_powf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN8vv_powf_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S index bdcabab..a32b66e 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN16vvv_sincosf) .type _ZGVeN16vvv_sincosf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN16vvv_sincosf_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16vvv_sincosf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN16vvv_sincosf_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN16vvv_sincosf_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S index 610046b..e64fbfb 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN4vvv_sincosf) .type _ZGVbN4vvv_sincosf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN4vvv_sincosf_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4vvv_sincosf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN4vvv_sincosf_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S index 9e5be67..b3f31c6 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN8vvv_sincosf) .type _ZGVdN8vvv_sincosf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVdN8vvv_sincosf_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVdN8vvv_sincosf_avx2(%rip), %rax + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN8vvv_sincosf_sse_wrapper(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S index 3ec78a0..c7a0adb 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S @@ -22,14 +22,12 @@ .text ENTRY (_ZGVeN16v_sinf) .type _ZGVeN16v_sinf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVeN16v_sinf_skx(%rip), %rax - testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVeN16v_sinf_skx(%rip), %rax + HAS_ARCH_FEATURE (AVX512DQ_Usable) jnz 2f leaq _ZGVeN16v_sinf_knl(%rip), %rax - testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip) + HAS_ARCH_FEATURE (AVX512F_Usable) jnz 2f leaq _ZGVeN16v_sinf_avx2_wrapper(%rip), %rax 2: ret diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S index cf1e4df..58bd177 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVbN4v_sinf) .type _ZGVbN4v_sinf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features -1: leaq _ZGVbN4v_sinf_sse4(%rip), %rax - testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip) + LOAD_RTLD_GLOBAL_RO_RDX + leaq _ZGVbN4v_sinf_sse4(%rip), %rax + HAS_CPU_FEATURE (SSE4_1) jz 2f ret 2: leaq _ZGVbN4v_sinf_sse2(%rip), %rax diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S index b28bf3c..debec59 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S @@ -22,11 +22,9 @@ .text ENTRY (_ZGVdN8v_sinf) .type _ZGVdN8v_sinf, @gnu_indirect_function - cmpl $0, KIND_OFFSET+__cpu_features(%rip) - jne 1f - call __init_cpu_features + LOAD_RTLD_GLOBAL_RO_RDX 1: leaq _ZGVdN8v_sinf_avx2(%rip), %rax - testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip) + HAS_ARCH_FEATURE (AVX2_Usable) jz 2f ret 2: leaq _ZGVdN8v_sinf_sse_wrapper(%rip), %rax |