[BZ #9726]

2009-01-11  Ryan S. Arnold  <rsa@us.ibm.com>
	[BZ #9726]
	* sysdeps/powerpc/fpu/tst-setcontext-fpscr.c (_SET_DI_FPSCR,
	_SET_SI_FPSCR): Clobber fp0 to prevent erroneous test-case passes.

2009-01-08  Ryan S. Arnold  <rsa@us.ibm.com>

	[BZ #9726]
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
	(__CONTEXT_FUNC_NAME): Fix mtfsf to use fp31 instead of fp0.
	* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
	(__CONTEXT_FUNC_NAME): Fix mtfsf to use fp31 instead of fp0.

3 files changed, 25 insertions, 19 deletions

diff --git a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
index 973fb3f..a15fe86 100644
--- a/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
+++ b/sysdeps/powerpc/fpu/tst-setcontext-fpscr.c
@@ -1,4 +1,4 @@
-/* Copyright (C) 2001,2002,2004,2006,2007,2008 Free Software Foundation, Inc.
+/* Copyright (C) 2001,2002,2004,2006-2008,2009 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
    Contributed by Ryan S. Arnold <rsa@us.ibm.com>
                   Sean Curry <spcurry@us.ibm.com>
@@ -104,12 +104,16 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__)));
    (__fpscr)=tmp.fpscr;							     \
    tmp.fpscr; })
 
+/* We make sure to zero fp0 after we use it in order to prevent stale data
+   in an fp register from making a test-case pass erroneously.  */
 # define _SET_DI_FPSCR(__fpscr) {					     \
   union { double d; di_fpscr_t fpscr; }					     \
     tmp __attribute__ ((__aligned__(8)));				     \
   tmp.fpscr = __fpscr;							     \
   /* Set the entire 64-bit FPSCR.  */					     \
   __asm__ ("lfd%U0 0,%0; mtfsf 255,0,1,0" : : "m" (tmp.d) : "fr0");	     \
+  tmp.d = 0;								     \
+  __asm__("lfd%U0 0,%0" : : "m" (tmp.d) : "fr0");			     \
 }
 
 # define _GET_SI_FPSCR(__fpscr) ({					     \
@@ -120,6 +124,8 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__)));
    (__fpscr)=tmp.cw[1];							     \
    tmp.cw[0]; })
 
+/* We make sure to zero fp0 after we use it in order to prevent stale data
+   in an fp register from making a test-case pass erroneously.  */
 # define _SET_SI_FPSCR(__fpscr) {					     \
   union { double d; si_fpscr_t fpscr[2]; }				     \
     tmp __attribute__ ((__aligned__(8)));				     \
@@ -127,6 +133,8 @@ typedef unsigned int si_fpscr_t __attribute__ ((__mode__ (__SI__)));
   tmp.fpscr[0] = 0xFFF80000;						     \
   tmp.fpscr[1] = __fpscr;						     \
   __asm__ ("lfd%U0 0,%0; mtfsf 255,0" : : "m" (tmp.d) : "fr0");		     \
+  tmp.d = 0;								     \
+  __asm__("lfd%U0 0,%0" : : "m" (tmp.d) : "fr0");			     \
 }
 
 void prime_special_regs(int which)
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
index 91ac436..d83a0ef 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S
@@ -1,5 +1,5 @@
 /* Jump to a new context powerpc32 common.
-   Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
+   Copyright (C) 2005, 2006, 2008, 2009 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -18,13 +18,13 @@
    02110-1301 USA.  */
 
 /* This is the common implementation of setcontext for powerpc32.
-   It not complete in itself should be included in to a framework that 
+   It not complete in itself should be included in to a framework that
    defines:
      __CONTEXT_FUNC_NAME
    and if appropriate:
      __CONTEXT_ENABLE_FPRS
      __CONTEXT_ENABLE_VRS
-   Any archecture that implements the Vector unit is assumed to also 
+   Any archecture that implements the Vector unit is assumed to also
    implement the floating unit.  */
 
 /* Stack frame offsets.  */
@@ -202,7 +202,7 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	lfd	fp0,_UC_FREGS+(0*8)(r31)
 # ifdef _ARCH_PWR6
 	/* Use the extended four-operand version of the mtfsf insn.  */
-	mtfsf  0xff,fp0,1,0
+	mtfsf	0xff,fp31,1,0
 # else
 	/* Availability of DFP indicates a 64-bit FPSCR.  */
 	andi.	r6,r7,PPC_FEATURE_HAS_DFP
@@ -304,4 +304,3 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	/* NOTREACHED */
 
 END (__CONTEXT_FUNC_NAME)
-
diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
index 77c9822..243a66a 100644
--- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
+++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S
@@ -1,5 +1,5 @@
 /* Save current context and jump to a new context.
-   Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc.
+   Copyright (C) 2005, 2006, 2008, 2009 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -18,13 +18,13 @@
    02110-1301 USA.  */
 
 /* This is the common implementation of setcontext for powerpc32.
-   It not complete in itself should be included in to a framework that 
+   It not complete in itself should be included in to a framework that
    defines:
      __CONTEXT_FUNC_NAME
    and if appropriate:
      __CONTEXT_ENABLE_FPRS
      __CONTEXT_ENABLE_VRS
-   Any archecture that implements the Vector unit is assumed to also 
+   Any archecture that implements the Vector unit is assumed to also
    implement the floating unit.  */
 
 /* Stack frame offsets.  */
@@ -51,7 +51,7 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	stw	r0,_UC_GREGS+(PT_R0*4)(r3)
 	mflr	r0
 	stw	r2,_UC_GREGS+(PT_R2*4)(r3)
-	stw	r4,_UC_GREGS+(PT_R4*4)(r3)			
+	stw	r4,_UC_GREGS+(PT_R4*4)(r3)
 /* Set the callers LR_SAVE, and the ucontext LR and NIP to the callers
    return address.  */
 	stw	r0,_UC_GREGS+(PT_LNK*4)(r3)
@@ -85,7 +85,7 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	stw	r29,_UC_GREGS+(PT_R29*4)(r3)
 	stw	r30,_UC_GREGS+(PT_R30*4)(r3)
 	stw	r31,_UC_GREGS+(PT_R31*4)(r3)
-	
+
 /* Save the value of R1.  We had to push the stack before we
    had the address of uc_reg_space.  So compute the address of
    the callers stack pointer and save it as R1.  */
@@ -174,10 +174,10 @@ ENTRY(__CONTEXT_FUNC_NAME)
 
 	la	r10,(_UC_VREGS)(r3)
 	la	r9,(_UC_VREGS+16)(r3)
-	
+
 /*	beq	L(no_vec)*/
 	beq	2f
-/* address of the combined VSCR/VSAVE quadword.  */	
+/* address of the combined VSCR/VSAVE quadword.  */
 	la	r8,(_UC_VREGS+512)(r3)
 
 /* Save the vector registers */
@@ -194,7 +194,7 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	stvx  v3,0,r9
 	addi  r10,r10,32
 	addi  r9,r9,32
-	
+
 	stvx	v0,0,r8
 
 	stvx  v4,0,r10
@@ -266,7 +266,7 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	stvx  v30,0,r10
 	stvx  v31,0,r9
  	stw	r0,0(r8)
-	
+
 2: /*L(no_vec):*/
 # endif /* __CONTEXT_ENABLE_VRS */
 #endif /* __CONTEXT_ENABLE_FPRS */
@@ -428,7 +428,7 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	lfd	fp0,_UC_FREGS+(0*8)(r31)
 # ifdef _ARCH_PWR6
 	/* Use the extended four-operand version of the mtfsf insn.  */
-	mtfsf  0xff,fp0,1,0
+	mtfsf	0xff,fp31,1,0
 # else
 	/* Availability of DFP indicates a 64-bit FPSCR.  */
 	andi.	r6,r7,PPC_FEATURE_HAS_DFP
@@ -514,13 +514,13 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	lwz	r31,_UC_GREGS+(PT_R31*4)(r31)
 
 	bctr
-	
+
 3:/*L(error_exit):*/
 	lwz	r0,_FRAME_LR_SAVE+16(r1)
 	addi	r1,r1,16
 	mtlr	r0
 	blr
-	
+
 4:/*L(do_sigret):*/
 	addi	r1,r4,-0xd0
 	li	r0,SYS_ify(rt_sigreturn)
@@ -528,4 +528,3 @@ ENTRY(__CONTEXT_FUNC_NAME)
 	/* NOTREACHED */
 
 END(__CONTEXT_FUNC_NAME)
-