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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-06-30 10:47:06 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-07-01 10:47:35 -0700 |
| commit | ea8e465a6b8d0f26c72bcbe453a854de3abf68ec (patch) | |
| tree | f0b6b62b393ea4715f75248e5425d088a8aeba14 /sysdeps/x86/include | |
| parent | b1b4f7209ecaad4bf9a5d0d2ef1338409d364bac (diff) | |
| download | glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.zip glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.tar.gz glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.tar.bz2 | |
x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
From
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
* Intel TSX will be disabled by default.
* The processor will force abort all Restricted Transactional Memory (RTM)
transactions by default.
* A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
which is set to indicate to updated software that the loaded microcode is
forcing RTM abort.
* On processors that enumerate support for RTM, the CPUID enumeration bits
for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
be set by default after microcode update.
* Workloads that were benefited from Intel TSX might experience a change
in performance.
* System software may use a new bit in Model-Specific Register (MSR) 0x10F
TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
Elision (HLE) and RTM bits to indicate to software that Intel TSX is
disabled.
1. Add RTM_ALWAYS_ABORT to CPUID features.
2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the
string/tst-memchr-rtm etc. testcases on the affected processors, which
always fail after a microcde update.
3. Check RTM feature, instead of usability, against /proc/cpuinfo.
This fixes BZ #28033.
Diffstat (limited to 'sysdeps/x86/include')
| -rw-r--r-- | sysdeps/x86/include/cpu-features.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index 4f1c4ee..59e01df 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -229,7 +229,7 @@ enum #define bit_cpu_AVX512_VP2INTERSECT (1u << 8) #define bit_cpu_INDEX_7_EDX_9 (1u << 9) #define bit_cpu_MD_CLEAR (1u << 10) -#define bit_cpu_INDEX_7_EDX_11 (1u << 11) +#define bit_cpu_RTM_ALWAYS_ABORT (1u << 11) #define bit_cpu_INDEX_7_EDX_12 (1u << 12) #define bit_cpu_INDEX_7_EDX_13 (1u << 13) #define bit_cpu_SERIALIZE (1u << 14) @@ -463,7 +463,7 @@ enum #define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7 #define index_cpu_MD_CLEAR CPUID_INDEX_7 -#define index_cpu_INDEX_7_EDX_11 CPUID_INDEX_7 +#define index_cpu_RTM_ALWAYS_ABORT CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7 #define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7 #define index_cpu_SERIALIZE CPUID_INDEX_7 @@ -697,7 +697,7 @@ enum #define reg_AVX512_VP2INTERSECT edx #define reg_INDEX_7_EDX_9 edx #define reg_MD_CLEAR edx -#define reg_INDEX_7_EDX_11 edx +#define reg_RTM_ALWAYS_ABORT edx #define reg_INDEX_7_EDX_12 edx #define reg_INDEX_7_EDX_13 edx #define reg_SERIALIZE edx |