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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-06-30 10:47:06 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-07-01 10:47:35 -0700 |
| commit | ea8e465a6b8d0f26c72bcbe453a854de3abf68ec (patch) | |
| tree | f0b6b62b393ea4715f75248e5425d088a8aeba14 /sysdeps/x86/cpu-features.c | |
| parent | b1b4f7209ecaad4bf9a5d0d2ef1338409d364bac (diff) | |
| download | glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.zip glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.tar.gz glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.tar.bz2 | |
x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
From
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
* Intel TSX will be disabled by default.
* The processor will force abort all Restricted Transactional Memory (RTM)
transactions by default.
* A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
which is set to indicate to updated software that the loaded microcode is
forcing RTM abort.
* On processors that enumerate support for RTM, the CPUID enumeration bits
for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
be set by default after microcode update.
* Workloads that were benefited from Intel TSX might experience a change
in performance.
* System software may use a new bit in Model-Specific Register (MSR) 0x10F
TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
Elision (HLE) and RTM bits to indicate to software that Intel TSX is
disabled.
1. Add RTM_ALWAYS_ABORT to CPUID features.
2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the
string/tst-memchr-rtm etc. testcases on the affected processors, which
always fail after a microcde update.
3. Check RTM feature, instead of usability, against /proc/cpuinfo.
This fixes BZ #28033.
Diffstat (limited to 'sysdeps/x86/cpu-features.c')
| -rw-r--r-- | sysdeps/x86/cpu-features.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index a1d8d11..563a206 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, HLE); CPU_FEATURE_SET_USABLE (cpu_features, BMI2); CPU_FEATURE_SET_USABLE (cpu_features, ERMS); - CPU_FEATURE_SET_USABLE (cpu_features, RTM); CPU_FEATURE_SET_USABLE (cpu_features, RDSEED); CPU_FEATURE_SET_USABLE (cpu_features, ADX); CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT); @@ -83,6 +82,7 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, MOVDIRI); CPU_FEATURE_SET_USABLE (cpu_features, MOVDIR64B); CPU_FEATURE_SET_USABLE (cpu_features, FSRM); + CPU_FEATURE_SET_USABLE (cpu_features, RTM_ALWAYS_ABORT); CPU_FEATURE_SET_USABLE (cpu_features, SERIALIZE); CPU_FEATURE_SET_USABLE (cpu_features, TSXLDTRK); CPU_FEATURE_SET_USABLE (cpu_features, LAHF64_SAHF64); @@ -97,6 +97,9 @@ update_usable (struct cpu_features *cpu_features) CPU_FEATURE_SET_USABLE (cpu_features, FSRCS); CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE); + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT)) + CPU_FEATURE_SET_USABLE (cpu_features, RTM); + #if CET_ENABLED CPU_FEATURE_SET_USABLE (cpu_features, IBT); CPU_FEATURE_SET_USABLE (cpu_features, SHSTK); |