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| author | Andrew Pinski <quic_apinski@quicinc.com> | 2024-06-12 15:53:36 -0700 |
|---|---|---|
| committer | Andreas K. Hüttel <dilfridge@gentoo.org> | 2024-06-30 13:47:17 +0200 |
| commit | 2f1f7a5f8aa7285e9a55b209dd01fdcb0d4e7281 (patch) | |
| tree | d905d50005692a91c90d953cb7f4f9b574530057 /sysdeps/x86/cpu-features.c | |
| parent | 4dc83cac78a92a99cdd1ae808890083461597b82 (diff) | |
| download | glibc-2f1f7a5f8aa7285e9a55b209dd01fdcb0d4e7281.zip glibc-2f1f7a5f8aa7285e9a55b209dd01fdcb0d4e7281.tar.gz glibc-2f1f7a5f8aa7285e9a55b209dd01fdcb0d4e7281.tar.bz2 | |
Aarch64: Add new memset for Qualcomm's oryon-1 core
Qualcom's new core, oryon-1, has a different characteristics for
memset than the current versions of memset. For non-zero, larger
sizes, using GPRs rather than the SIMD stores is ~30% faster.
For even larger sizes, using the nontemporal stores is needed
not to polute the L1/L2 caches.
For zero values, using `dc zva` should be used. Since we
know the size will always be 64 bytes, we don't need to figure
out the size there.
I started with the emag memset and added back the `dc zva` code.
Changes since v1:
* v3: Fix comment formating
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Diffstat (limited to 'sysdeps/x86/cpu-features.c')
0 files changed, 0 insertions, 0 deletions