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| author | Chris Metcalf <cmetcalf@ezchip.com> | 2015-01-28 14:51:21 -0500 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@ezchip.com> | 2015-01-28 14:51:21 -0500 |
| commit | 06991eb816c935961584eeba121e8930c036372f (patch) | |
| tree | 8db9d083e13575dba3577a2d7f29c51038c5fe8c /sysdeps/tile | |
| parent | df34134284b46cdd8ffd39551b858652d465ca08 (diff) | |
| download | glibc-06991eb816c935961584eeba121e8930c036372f.zip glibc-06991eb816c935961584eeba121e8930c036372f.tar.gz glibc-06991eb816c935961584eeba121e8930c036372f.tar.bz2 | |
tilegx32: set __HAVE_64B_ATOMICS to 0
This is because of alignment issues in the sem_t support.
tilegx32 does in fact support 64-bit atomics and we will need
to revisit this after the 2.21 freeze.
Diffstat (limited to 'sysdeps/tile')
| -rw-r--r-- | sysdeps/tile/tilegx/bits/atomic.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/sysdeps/tile/tilegx/bits/atomic.h b/sysdeps/tile/tilegx/bits/atomic.h index ac654b8..e75efb1 100644 --- a/sysdeps/tile/tilegx/bits/atomic.h +++ b/sysdeps/tile/tilegx/bits/atomic.h @@ -21,7 +21,15 @@ #include <arch/spr_def.h> -#define __HAVE_64B_ATOMICS 1 +#ifdef _LP64 +# define __HAVE_64B_ATOMICS 1 +#else +/* tilegx32 does have 64-bit atomics, but assumptions in the semaphore + code mean that unaligned 64-bit atomics will be used if this symbol + is true, and unaligned atomics are not supported on tile. */ +# define __HAVE_64B_ATOMICS 0 +#endif + #define USE_ATOMIC_COMPILER_BUILTINS 0 /* Pick appropriate 8- or 4-byte instruction. */ |