PowerPC: Fix __fe_nomask_env missing symbol

This patch fix the missing symbol __fe_nomask_env from commit
41e8926aa4b7f17bc95984737ee82a254ad0911c for GLIBC_2.1.

6 files changed, 9 insertions, 10 deletions

diff --git a/sysdeps/powerpc/fpu/fe_nomask.c b/sysdeps/powerpc/fpu/fe_nomask.c
index 5127000..f54c076 100644
--- a/sysdeps/powerpc/fpu/fe_nomask.c
+++ b/sysdeps/powerpc/fpu/fe_nomask.c
@@ -24,10 +24,9 @@
    normally involve a syscall.  */
 
 const fenv_t *
-__fe_nomask_env(void)
+__fe_nomask_env_priv (void)
 {
   __set_errno (ENOSYS);
   return FE_ENABLED_ENV;
 }
-libm_hidden_def (__fe_nomask_env)
-stub_warning (__fe_nomask_env)
+stub_warning (__fe_nomask_env_priv)
diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c
index 472796d..35e977e 100644
--- a/sysdeps/powerpc/fpu/feenablxcpt.c
+++ b/sysdeps/powerpc/fpu/feenablxcpt.c
@@ -45,7 +45,7 @@ feenableexcept (int excepts)
 
   new = __fegetexcept ();
   if (new != 0 && result == 0)
-    (void)__fe_nomask_env ();
+    (void) __fe_nomask_env_priv ();
 
   if ((new & excepts) != excepts)
     result = -1;
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index ecd6b91..74d633d 100644
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -23,7 +23,7 @@
 #include <ldsodefs.h>
 #include <sysdep.h>
 
-extern const fenv_t *__fe_nomask_env (void) attribute_hidden;
+extern const fenv_t *__fe_nomask_env_priv (void);
 
 extern const fenv_t *__fe_mask_env (void) attribute_hidden;
 
diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h
index 293f840..bc78c3f 100644
--- a/sysdeps/powerpc/fpu/fenv_private.h
+++ b/sysdeps/powerpc/fpu/fenv_private.h
@@ -96,7 +96,7 @@ libc_fesetenv_ppc (const fenv_t *envp)
      hardware into "precise mode" and may cause the FPU to run slower on some
      hardware.  */
   if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
-    (void) __fe_nomask_env ();
+    (void) __fe_nomask_env_priv ();
 
   /* If the old env had any enabled exceptions and the new env has no enabled
      exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
@@ -123,7 +123,7 @@ libc_feupdateenv_test_ppc (fenv_t *envp, int ex)
           | (new.l & _FPU_MASK_FRAC_INEX_RET_CC);
 
   if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
-    (void) __fe_nomask_env ();
+    (void) __fe_nomask_env_priv ();
 
   if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
     (void) __fe_mask_env ();
@@ -169,7 +169,7 @@ libc_feresetround_ppc (fenv_t *envp)
           | (new.l & _FPU_MASK_FRAC_INEX_RET_CC);
 
   if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
-    (void) __fe_nomask_env ();
+    (void) __fe_nomask_env_priv ();
 
   if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
     (void) __fe_mask_env ();
diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c
index 6c00b26..5de6ff5 100644
--- a/sysdeps/powerpc/fpu/fesetenv.c
+++ b/sysdeps/powerpc/fpu/fesetenv.c
@@ -35,7 +35,7 @@ __fesetenv (const fenv_t *envp)
      hardware into "precise mode" and may cause the FPU to run slower on some
      hardware.  */
   if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
-    (void)__fe_nomask_env ();
+    (void) __fe_nomask_env_priv ();
 
   /* If the old env had any enabled exceptions and the new env has no enabled
      exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c
index 6775044..262e213 100644
--- a/sysdeps/powerpc/fpu/feupdateenv.c
+++ b/sysdeps/powerpc/fpu/feupdateenv.c
@@ -41,7 +41,7 @@ __feupdateenv (const fenv_t *envp)
      the hardware into "precise mode" and may cause the FPU to run slower on
      some hardware.  */
   if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
-    (void)__fe_nomask_env ();
+    (void) __fe_nomask_env_priv ();
 
   /* If the old env had any enabled exceptions and the new env has no enabled
      exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the