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authorUlrich Drepper <drepper@redhat.com>2003-04-17 19:19:29 +0000
committerUlrich Drepper <drepper@redhat.com>2003-04-17 19:19:29 +0000
commit94c24227fcc1da2d12249e236f2fdde62253778d (patch)
tree2ad42af1f76891576bfce4a28b3825ae95552660 /sysdeps/powerpc
parent66cd688c01778d4f824de236c169e9cfb5c5f4e4 (diff)
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Update.
2003-04-16 Jakub Jelinek <jakub@redhat.com> * elf/Makefile (distribute): Add tst-tlsmod{[7-9],1[0-2]}.c and tst-tls10.h. (tests): Add tst-tls1[0-2]. (modules-names): Add tst-tlsmod{[7-8],1[0-2]}. ($(objpfx)tst-tlsmod8.so): Depend on tst-tlsmod7.so. ($(objpfx)tst-tlsmod10.so): Depend on tst-tlsmod9.so. ($(objpfx)tst-tlsmod12.so): Depend on tst-tlsmod11.so. ($(objpfx)tst-tls10): Depend on tst-tlsmod8.so. ($(objpfx)tst-tls11): Depend on tst-tlsmod10.so. ($(objpfx)tst-tls12): Depend on tst-tlsmod12.so. * elf/tst-tls10.c: New test. * elf/tst-tls11.c: New test. * elf/tst-tls12.c: New test. * elf/tst-tls10.h: New file. * elf/tst-tlsmod7.c: New file. * elf/tst-tlsmod8.c: New file. * elf/tst-tlsmod9.c: New file. * elf/tst-tlsmod10.c: New file. * elf/tst-tlsmod11.c: New file. * elf/tst-tlsmod12.c: New file. 2003-04-15 Steven Munroe <sjmunroe@us.ibm.com> * sysdeps/powerpc/bits/atomic.h: Moved ppc32/64 specific code to ... * sysdeps/powerpc/powerpc32/bits/atomic.h: New file. * sysdeps/powerpc/powerpc64/bits/atomic.h: New file. * posix/regex.h: Include <sys/types.h>.
Diffstat (limited to 'sysdeps/powerpc')
-rw-r--r--sysdeps/powerpc/bits/atomic.h172
-rw-r--r--sysdeps/powerpc/powerpc32/bits/atomic.h75
-rw-r--r--sysdeps/powerpc/powerpc64/bits/atomic.h135
3 files changed, 227 insertions, 155 deletions
diff --git a/sysdeps/powerpc/bits/atomic.h b/sysdeps/powerpc/bits/atomic.h
index d4a910f..c33ae56 100644
--- a/sysdeps/powerpc/bits/atomic.h
+++ b/sysdeps/powerpc/bits/atomic.h
@@ -1,4 +1,4 @@
-/* Atomic operations. PowerPC version.
+/* Atomic operations. PowerPC Common version.
Copyright (C) 2003 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
@@ -18,17 +18,16 @@
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
-#include <stdint.h>
-
-typedef int8_t atomic8_t;
-typedef uint8_t uatomic8_t;
-typedef int_fast8_t atomic_fast8_t;
-typedef uint_fast8_t uatomic_fast8_t;
+/*
+ * Never include sysdeps/powerpc/bits/atomic.h directly.
+ * Alway use include/atomic.h which will include either
+ * sysdeps/powerpc/powerpc32/bits/atomic.h
+ * or
+ * sysdeps/powerpc/powerpc64/bits/atomic.h
+ * as appropriate and which in turn include this file.
+ */
-typedef int16_t atomic16_t;
-typedef uint16_t uatomic16_t;
-typedef int_fast16_t atomic_fast16_t;
-typedef uint_fast16_t uatomic_fast16_t;
+#include <stdint.h>
typedef int32_t atomic32_t;
typedef uint32_t uatomic32_t;
@@ -45,7 +44,10 @@ typedef uintptr_t uatomicptr_t;
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;
-
+/*
+ * Powerpc does not have byte and halfword forms of load and reserve and
+ * store conditional. So for powerpc we stub out the 8- and 16-bit forms.
+ */
#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
(abort (), 0)
@@ -60,146 +62,14 @@ typedef uintmax_t uatomic_max_t;
# define __ARCH_REL_INSTR "sync"
#endif
+#define atomic_full_barrier() __asm ("sync" ::: "memory")
+#define atomic_write_barrier() __asm ("eieio" ::: "memory")
+
/*
* XXX At present these have both acquire and release semantics.
* Ultimately we should do separate _acq and _rel versions.
*/
-#ifdef __powerpc64__
-
-/*
- * The 32-bit exchange_bool is different on powerpc64 because the subf
- * does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
- * (a load word and zero (high 32) form).
- * In powerpc64 register values are 64-bit by default, including oldval.
- * Net we need to extend sign word the result of lwarx to 64-bit so the
- * 64-bit subtract from gives the expected result and sets the condition
- * correctly.
- */
-# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
-({ \
- unsigned int __tmp; \
- __asm __volatile (__ARCH_REL_INSTR "\n" \
- "1: lwarx %0,0,%1\n" \
- " extsw %0,%0\n" \
- " subf. %0,%2,%0\n" \
- " bne 2f\n" \
- " stwcx. %3,0,%1\n" \
- " bne- 1b\n" \
- "2: " __ARCH_ACQ_INSTR \
- : "=&r" (__tmp) \
- : "b" (mem), "r" (oldval), "r" (newval) \
- : "cr0", "memory"); \
- __tmp != 0; \
-})
-
-# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
-({ \
- unsigned long __tmp; \
- __asm __volatile (__ARCH_REL_INSTR "\n" \
- "1: ldarx %0,0,%1\n" \
- " subf. %0,%2,%0\n" \
- " bne 2f\n" \
- " stdcx. %3,0,%1\n" \
- " bne- 1b\n" \
- "2: " __ARCH_ACQ_INSTR \
- : "=&r" (__tmp) \
- : "b" (mem), "r" (oldval), "r" (newval) \
- : "cr0", "memory"); \
- __tmp != 0; \
-})
-
-#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
- ({ \
- __typeof (*(mem)) __tmp; \
- __typeof (mem) __memp = (mem); \
- __asm __volatile (__ARCH_REL_INSTR "\n" \
- "1: ldarx %0,0,%1\n" \
- " cmpd %0,%2\n" \
- " bne 2f\n" \
- " stdcx. %3,0,%1\n" \
- " bne- 1b\n" \
- "2: " __ARCH_ACQ_INSTR \
- : "=&r" (__tmp) \
- : "b" (__memp), "r" (oldval), "r" (newval) \
- : "cr0", "memory"); \
- __tmp; \
- })
-
-# define __arch_atomic_exchange_64(mem, value) \
- ({ \
- __typeof (*mem) __val; \
- __asm __volatile (__ARCH_REL_INSTR "\n" \
- "1: ldarx %0,0,%2\n" \
- " stdcx. %3,0,%2\n" \
- " bne- 1b" \
- : "=&r" (__val), "=m" (*mem) \
- : "b" (mem), "r" (value), "1" (*mem) \
- : "cr0"); \
- __val; \
- })
-
-# define __arch_atomic_exchange_and_add_64(mem, value) \
- ({ \
- __typeof (*mem) __val, __tmp; \
- __asm __volatile ("1: ldarx %0,0,%3\n" \
- " add %1,%0,%4\n" \
- " stdcx. %1,0,%3\n" \
- " bne- 1b" \
- : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
- : "b" (mem), "r" (value), "2" (*mem) \
- : "cr0"); \
- __val; \
- })
-
-# define __arch_atomic_decrement_if_positive_64(mem) \
- ({ int __val, __tmp; \
- __asm __volatile ("1: ldarx %0,0,%3\n" \
- " cmpdi 0,%0,0\n" \
- " addi %1,%0,-1\n" \
- " ble 2f\n" \
- " stdcx. %1,0,%3\n" \
- " bne- 1b\n" \
- "2: " __ARCH_ACQ_INSTR \
- : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
- : "b" (mem), "2" (*mem) \
- : "cr0"); \
- __val; \
- })
-
-#else /* powerpc32 */
-# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
-({ \
- unsigned int __tmp; \
- __asm __volatile (__ARCH_REL_INSTR "\n" \
- "1: lwarx %0,0,%1\n" \
- " subf. %0,%2,%0\n" \
- " bne 2f\n" \
- " stwcx. %3,0,%1\n" \
- " bne- 1b\n" \
- "2: " __ARCH_ACQ_INSTR \
- : "=&r" (__tmp) \
- : "b" (mem), "r" (oldval), "r" (newval) \
- : "cr0", "memory"); \
- __tmp != 0; \
-})
-
-# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
- (abort (), 0)
-
-# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
- (abort (), 0)
-
-# define __arch_atomic_exchange_64(mem, value) \
- ({ abort (); (*mem) = (value); })
-
-# define __arch_atomic_exchange_and_add_64(mem, value) \
- ({ abort (); (*mem) = (value); })
-
-# define __arch_atomic_decrement_if_positive_64(mem) \
- ({ abort (); (*mem)--; })
-#endif
-
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \
@@ -308,11 +178,3 @@ typedef uintmax_t uatomic_max_t;
__result; \
})
-
-#define atomic_full_barrier() __asm ("sync" ::: "memory")
-#ifdef __powerpc64__
-# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
-#else
-# define atomic_read_barrier() __asm ("sync" ::: "memory")
-#endif
-#define atomic_write_barrier() __asm ("eieio" ::: "memory")
diff --git a/sysdeps/powerpc/powerpc32/bits/atomic.h b/sysdeps/powerpc/powerpc32/bits/atomic.h
new file mode 100644
index 0000000..9e56184
--- /dev/null
+++ b/sysdeps/powerpc/powerpc32/bits/atomic.h
@@ -0,0 +1,75 @@
+/* Atomic operations. PowerPC32 version.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+/*
+ * The 32-bit exchange_bool is different on powerpc64 because the subf
+ * does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
+ * (a load word and zero (high 32) form). So powerpc64 has a slightly
+ * different version in sysdeps/powerpc/powerpc64/bits/atomic.h.
+ */
+# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
+({ \
+ unsigned int __tmp; \
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
+ "1: lwarx %0,0,%1\n" \
+ " subf. %0,%2,%0\n" \
+ " bne 2f\n" \
+ " stwcx. %3,0,%1\n" \
+ " bne- 1b\n" \
+ "2: " __ARCH_ACQ_INSTR \
+ : "=&r" (__tmp) \
+ : "b" (mem), "r" (oldval), "r" (newval) \
+ : "cr0", "memory"); \
+ __tmp != 0; \
+})
+
+/*
+ * Powerpc32 processors don't implement the 64-bit (doubleword) forms of
+ * load and reserve (ldarx) and store conditional (stdcx.) instructions.
+ * So for powerpc32 we stub out the 64-bit forms.
+ */
+# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
+ (abort (), 0)
+
+# define __arch_atomic_exchange_64(mem, value) \
+ ({ abort (); (*mem) = (value); })
+
+# define __arch_atomic_exchange_and_add_64(mem, value) \
+ ({ abort (); (*mem) = (value); })
+
+# define __arch_atomic_decrement_if_positive_64(mem) \
+ ({ abort (); (*mem)--; })
+
+/*
+ * Older powerpc32 processors don't support the new "light weight"
+ * sync (lwsync). So the only safe option is to use normal sync
+ * for all powerpc32 applications.
+ */
+# define atomic_read_barrier() __asm ("sync" ::: "memory")
+
+/*
+ * Include the rest of the atomic ops macros which are common to both
+ * powerpc32 and powerpc64.
+ */
+#include_next <bits/atomic.h>
+
diff --git a/sysdeps/powerpc/powerpc64/bits/atomic.h b/sysdeps/powerpc/powerpc64/bits/atomic.h
new file mode 100644
index 0000000..938e5ee
--- /dev/null
+++ b/sysdeps/powerpc/powerpc64/bits/atomic.h
@@ -0,0 +1,135 @@
+/* Atomic operations. PowerPC64 version.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307 USA. */
+
+/*
+ * The 32-bit exchange_bool is different on powerpc64 because the subf
+ * does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
+ * (a load word and zero (high 32) form) load.
+ * In powerpc64 register values are 64-bit by default, including oldval.
+ * Net we need to extend sign word the result of lwarx to 64-bit so the
+ * 64-bit subtract from gives the expected result and sets the condition
+ * correctly.
+ */
+# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
+({ \
+ unsigned int __tmp; \
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
+ "1: lwarx %0,0,%1\n" \
+ " extsw %0,%0\n" \
+ " subf. %0,%2,%0\n" \
+ " bne 2f\n" \
+ " stwcx. %3,0,%1\n" \
+ " bne- 1b\n" \
+ "2: " __ARCH_ACQ_INSTR \
+ : "=&r" (__tmp) \
+ : "b" (mem), "r" (oldval), "r" (newval) \
+ : "cr0", "memory"); \
+ __tmp != 0; \
+})
+
+/*
+ * Only powerpc64 processors support Load doubleword and reserve index (ldarx)
+ * and Store doubleword conditional indexed (stdcx) instructions. So here
+ * we define the 64-bit forms.
+ */
+# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
+({ \
+ unsigned long __tmp; \
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
+ "1: ldarx %0,0,%1\n" \
+ " subf. %0,%2,%0\n" \
+ " bne 2f\n" \
+ " stdcx. %3,0,%1\n" \
+ " bne- 1b\n" \
+ "2: " __ARCH_ACQ_INSTR \
+ : "=&r" (__tmp) \
+ : "b" (mem), "r" (oldval), "r" (newval) \
+ : "cr0", "memory"); \
+ __tmp != 0; \
+})
+
+#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
+ ({ \
+ __typeof (*(mem)) __tmp; \
+ __typeof (mem) __memp = (mem); \
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
+ "1: ldarx %0,0,%1\n" \
+ " cmpd %0,%2\n" \
+ " bne 2f\n" \
+ " stdcx. %3,0,%1\n" \
+ " bne- 1b\n" \
+ "2: " __ARCH_ACQ_INSTR \
+ : "=&r" (__tmp) \
+ : "b" (__memp), "r" (oldval), "r" (newval) \
+ : "cr0", "memory"); \
+ __tmp; \
+ })
+
+# define __arch_atomic_exchange_64(mem, value) \
+ ({ \
+ __typeof (*mem) __val; \
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
+ "1: ldarx %0,0,%2\n" \
+ " stdcx. %3,0,%2\n" \
+ " bne- 1b" \
+ : "=&r" (__val), "=m" (*mem) \
+ : "b" (mem), "r" (value), "1" (*mem) \
+ : "cr0"); \
+ __val; \
+ })
+
+# define __arch_atomic_exchange_and_add_64(mem, value) \
+ ({ \
+ __typeof (*mem) __val, __tmp; \
+ __asm __volatile ("1: ldarx %0,0,%3\n" \
+ " add %1,%0,%4\n" \
+ " stdcx. %1,0,%3\n" \
+ " bne- 1b" \
+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
+ : "b" (mem), "r" (value), "2" (*mem) \
+ : "cr0"); \
+ __val; \
+ })
+
+# define __arch_atomic_decrement_if_positive_64(mem) \
+ ({ int __val, __tmp; \
+ __asm __volatile ("1: ldarx %0,0,%3\n" \
+ " cmpdi 0,%0,0\n" \
+ " addi %1,%0,-1\n" \
+ " ble 2f\n" \
+ " stdcx. %1,0,%3\n" \
+ " bne- 1b\n" \
+ "2: " __ARCH_ACQ_INSTR \
+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
+ : "b" (mem), "2" (*mem) \
+ : "cr0"); \
+ __val; \
+ })
+
+/*
+ * All powerpc64 processors support the new "light weight" sync (lwsync).
+ */
+# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
+
+/*
+ * Include the rest of the atomic ops macros which are common to both
+ * powerpc32 and powerpc64.
+ */
+#include_next <bits/atomic.h>