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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 09:43:51 -0600 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 12:58:32 -0600 |
| commit | 487972aea52004f604c2878c8c9d3e77670f2c32 (patch) | |
| tree | 1f8a570e52975d04c513523e7d7b454a29015993 /sysdeps/powerpc/powerpc64/power8 | |
| parent | 7d92b78723848ae616709eb8f0191ea067025b18 (diff) | |
| download | glibc-487972aea52004f604c2878c8c9d3e77670f2c32.zip glibc-487972aea52004f604c2878c8c9d3e77670f2c32.tar.gz glibc-487972aea52004f604c2878c8c9d3e77670f2c32.tar.bz2 | |
PowerPC: Optimized isnan/isnanf for POWER8
This patch add a optimized isnan/isnanf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/power8')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S | 53 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S | 1 |
2 files changed, 54 insertions, 0 deletions
diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S new file mode 100644 index 0000000..c1ca9a5 --- /dev/null +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S @@ -0,0 +1,53 @@ +/* isnan(). PowerPC64/POWER8 version. + Copyright (C) 2014 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + +#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */ + +/* int [r3] __isnan([f1] x) */ + +EALIGN (__isnan, 4, 0) + CALL_MCOUNT 0 + MFVSRD_R3_V1 + lis r9,0x7ff0 + clrldi r3,r3,1 /* r3 = r3 & 0x8000000000000000 */ + rldicr r9,r9,32,31 /* r9 = (r9 << 32) & 0xffffffff */ + subf r3,r3,r9 + rldicl r3,r3,1,63 + blr +END (__isnan) + +/* It turns out that the 'double' version will also always work for + single-precision. */ +strong_alias (__isnan, __isnanf) +hidden_def (__isnanf) +weak_alias (__isnanf, isnanf) + +#ifdef NO_LONG_DOUBLE +strong_alias (__isnan, __isnanl) +weak_alias (__isnan, isnanl) +#endif + +#ifndef IS_IN_libm +# if LONG_DOUBLE_COMPAT(libc, GLIBC_2_0) +compat_symbol (libc, __isnan, __isnanl, GLIBC_2_0); +compat_symbol (libc, isnan, isnanl, GLIBC_2_0); +# endif +#endif diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S new file mode 100644 index 0000000..b48c85e --- /dev/null +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S @@ -0,0 +1 @@ +/* This function uses the same code as s_isnan.S. */ |