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authorJoseph Myers <joseph@codesourcery.com>2013-06-05 20:44:03 +0000
committerJoseph Myers <joseph@codesourcery.com>2013-06-05 20:44:03 +0000
commit9c84384cc18ff589233628c193953ca8d7a39f5c (patch)
tree95d1f5aee409b208db7545d678012eeae9559fae /sysdeps/powerpc/fpu/fesetenv.c
parent5556231db2301917cd14a7450de4eba2368c9763 (diff)
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Remove trailing whitespace.
Diffstat (limited to 'sysdeps/powerpc/fpu/fesetenv.c')
-rw-r--r--sysdeps/powerpc/fpu/fesetenv.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c
index 953af5d..e92adb4 100644
--- a/sysdeps/powerpc/fpu/fesetenv.c
+++ b/sysdeps/powerpc/fpu/fesetenv.c
@@ -29,21 +29,21 @@ __fesetenv (const fenv_t *envp)
/* get the currently set exceptions. */
new.fenv = *envp;
old.fenv = fegetenv_register ();
-
+
/* If the old env has no enabled exceptions and the new env has any enabled
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
hardware into "precise mode" and may cause the FPU to run slower on some
hardware. */
if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
(void)__fe_nomask_env ();
-
+
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
- FPU to run faster because it always takes the default action and can not
+ FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
(void)__fe_mask_env ();
-
+
fesetenv_register (*envp);
/* Success. */