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| author | Anton Blanchard <anton@au1.ibm.com> | 2013-08-17 18:28:55 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2013-10-04 10:34:26 +0930 |
| commit | 4a28b3ca4bc52d9a3ac0d9edb53d3de510e1b77c (patch) | |
| tree | b8a0550a21b55b508601d29a0615124be7354760 /sysdeps/powerpc/fpu/fesetenv.c | |
| parent | 2ca85d2bbbaa60b9c83bf1f57a2801c84e0a3625 (diff) | |
| download | glibc-4a28b3ca4bc52d9a3ac0d9edb53d3de510e1b77c.zip glibc-4a28b3ca4bc52d9a3ac0d9edb53d3de510e1b77c.tar.gz glibc-4a28b3ca4bc52d9a3ac0d9edb53d3de510e1b77c.tar.bz2 | |
PowerPC floating point little-endian [8 of 15]
http://sourceware.org/ml/libc-alpha/2013-07/msg00199.html
Corrects floating-point environment code for little-endian.
* sysdeps/powerpc/fpu/fenv_libc.h (fenv_union_t): Replace int
array with long long.
* sysdeps/powerpc/fpu/e_sqrt.c (__slow_ieee754_sqrt): Adjust.
* sysdeps/powerpc/fpu/e_sqrtf.c (__slow_ieee754_sqrtf): Adjust.
* sysdeps/powerpc/fpu/fclrexcpt.c (__feclearexcept): Adjust.
* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Adjust.
* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Adjust.
* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Adjust.
* sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Adjust.
* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Adjust.
* sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Adjust.
* sysdeps/powerpc/fpu/fgetexcptflg.c (__fegetexceptflag): Adjust.
* sysdeps/powerpc/fpu/fraiseexcpt.c (__feraiseexcept): Adjust.
* sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Adjust.
* sysdeps/powerpc/fpu/ftestexcept.c (fetestexcept): Adjust.
Diffstat (limited to 'sysdeps/powerpc/fpu/fesetenv.c')
| -rw-r--r-- | sysdeps/powerpc/fpu/fesetenv.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index e92adb4..6c00b26 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -34,14 +34,14 @@ __fesetenv (const fenv_t *envp) exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ - if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) + if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ - if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) + if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); fesetenv_register (*envp); |