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authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>2013-11-26 07:25:08 -0600
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>2013-11-26 07:25:08 -0600
commitbd12ab55c05ec80f1fd0df0997b26526295bbac7 (patch)
treeeaad2413dc537f0d83d6a2876cf13972cf403c47 /sysdeps/powerpc/fpu/fenv_private.h
parent52bb65431f7e3aa66a8bfc86919b0a4bacfe4a54 (diff)
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PowerPC: Fix __fe_nomask_env missing symbol
This patch fix the missing symbol __fe_nomask_env from commit 41e8926aa4b7f17bc95984737ee82a254ad0911c for GLIBC_2.1.
Diffstat (limited to 'sysdeps/powerpc/fpu/fenv_private.h')
-rw-r--r--sysdeps/powerpc/fpu/fenv_private.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h
index 293f840..bc78c3f 100644
--- a/sysdeps/powerpc/fpu/fenv_private.h
+++ b/sysdeps/powerpc/fpu/fenv_private.h
@@ -96,7 +96,7 @@ libc_fesetenv_ppc (const fenv_t *envp)
hardware into "precise mode" and may cause the FPU to run slower on some
hardware. */
if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
- (void) __fe_nomask_env ();
+ (void) __fe_nomask_env_priv ();
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
@@ -123,7 +123,7 @@ libc_feupdateenv_test_ppc (fenv_t *envp, int ex)
| (new.l & _FPU_MASK_FRAC_INEX_RET_CC);
if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
- (void) __fe_nomask_env ();
+ (void) __fe_nomask_env_priv ();
if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
(void) __fe_mask_env ();
@@ -169,7 +169,7 @@ libc_feresetround_ppc (fenv_t *envp)
| (new.l & _FPU_MASK_FRAC_INEX_RET_CC);
if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
- (void) __fe_nomask_env ();
+ (void) __fe_nomask_env_priv ();
if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
(void) __fe_mask_env ();