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authorPaul A. Clarke <pc@us.ibm.com>2019-07-18 19:37:13 -0500
committerPaul A. Clarke <pc@us.ibm.com>2019-08-28 13:50:06 -0500
commit3c1766ea10043f2e9625f3cba3bda37c84b32cf0 (patch)
treee3129c9f15b4db54ccdada2bad4dbe5365b34b7d /sysdeps/powerpc/fpu/feenablxcpt.c
parentcd7ce12a027656ad3cda774454088de5a2c7fbfa (diff)
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[powerpc] fe{en,dis}ableexcept, fesetmode: optimize FPSCR accesses
Since fe{en,dis}ableexcept() and fesetmode() read-modify-write just the "mode" (exception enable and rounding mode) bits of the Floating Point Status Control Register (FPSCR), the lighter weight 'mffsl' instruction can be used to read the FPSCR (enables and rounding mode), and 'mtfsf 0b00000011' can be used to write just those bits back to the FPSCR. The net is better performance. In addition, fe{en,dis}ableexcept() read the FPSCR again after writing it, or they determine that it doesn't need to be written because it is not changing. In either case, the local variable holds the current values of the enable bits in the FPSCR. This local variable can be used instead of again reading the FPSCR. Also, that value of the FPSCR which is read the second time is validated against the requested enables. Since the write can't fail, this validation step is unnecessary, and can be removed. Instead, the exceptions to be enabled (or disabled) are transformed into available bits in the FPSCR, then validated after being transformed back, to ensure that all requested bits are actually being set. For example, FE_INVALID_SQRT can be requested, but cannot actually be set. This bit is not mapped during the transformations, so a test for that bit being set before and after transformations will show the bit would not be set, and the function will return -1 for failure. Finally, convert the local macros in fesetmode.c to more generally useful macros in fenv_libc.h.
Diffstat (limited to 'sysdeps/powerpc/fpu/feenablxcpt.c')
-rw-r--r--sysdeps/powerpc/fpu/feenablxcpt.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c
index 3b64398..c06a7fd 100644
--- a/sysdeps/powerpc/fpu/feenablxcpt.c
+++ b/sysdeps/powerpc/fpu/feenablxcpt.c
@@ -26,24 +26,25 @@ feenableexcept (int excepts)
int result, new;
/* Get current exception mask to return. */
- fe.fenv = curr.fenv = fegetenv_register ();
+ fe.fenv = curr.fenv = fegetenv_status ();
result = fenv_reg_to_exceptions (fe.l);
if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID)
excepts = (excepts | FE_INVALID) & ~ FE_ALL_INVALID;
+ new = fenv_exceptions_to_reg (excepts);
+
+ if (fenv_reg_to_exceptions (new) != excepts)
+ return -1;
+
/* Sets the new exception mask. */
- fe.l |= fenv_exceptions_to_reg (excepts);
+ fe.l |= new;
if (fe.l != curr.l)
- fesetenv_register (fe.fenv);
+ fesetenv_mode (fe.fenv);
- new = __fegetexcept ();
if (new != 0 && result == 0)
(void) __fe_nomask_env_priv ();
- if ((new & excepts) != excepts)
- result = -1;
-
return result;
}