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author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-28 14:38:24 -0500 |
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committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-29 07:05:39 -0500 |
commit | 18f2945ae9216cfcd53a162080a73e3d719de9e6 (patch) | |
tree | 8d529fe01c41f0d3c6dd290aa69dbf4e5d6e083f /sysdeps/powerpc/fpu/feenablxcpt.c | |
parent | 5abebba403181de898bbea4ee1bcce5f088c663b (diff) | |
download | glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.zip glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.gz glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.bz2 |
PowerPC: Suppress unnecessary FPSCR write
This patch optimizes the FPSCR update on exception and rounding change
functions by just updating its value if new value if different from
current one. It also optimizes fedisableexcept and feenableexcept by
removing an unecessary FPSCR read.
Diffstat (limited to 'sysdeps/powerpc/fpu/feenablxcpt.c')
-rw-r--r-- | sysdeps/powerpc/fpu/feenablxcpt.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index 8ad0f97..01a68cf 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -22,15 +22,17 @@ int feenableexcept (int excepts) { - fenv_union_t fe; - int result, new; + fenv_union_t fe, curr; + int result = 0, new; - result = __fegetexcept (); + /* Get current exception mask to return. */ + fe.fenv = curr.fenv = fegetenv_register (); + result = fenv_reg_to_exceptions (fe.l); if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID) excepts = (excepts | FE_INVALID) & ~ FE_ALL_INVALID; - fe.fenv = fegetenv_register (); + /* Sets the new exception mask. */ if (excepts & FE_INEXACT) fe.l |= (1 << (31 - FPSCR_XE)); if (excepts & FE_DIVBYZERO) @@ -41,7 +43,9 @@ feenableexcept (int excepts) fe.l |= (1 << (31 - FPSCR_OE)); if (excepts & FE_INVALID) fe.l |= (1 << (31 - FPSCR_VE)); - fesetenv_register (fe.fenv); + + if (fe.l != curr.l) + fesetenv_register (fe.fenv); new = __fegetexcept (); if (new != 0 && result == 0) |