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authorUlrich Drepper <drepper@redhat.com>2003-03-20 10:18:24 +0000
committerUlrich Drepper <drepper@redhat.com>2003-03-20 10:18:24 +0000
commitf79466a8e909930237d882da8916bbbb1401edf6 (patch)
tree460afefe452e8550b56d9a01d90dc129012dfd27 /sysdeps/powerpc/bits
parent5132931e18d50a1caf7399aa46dafd0142a7c7ae (diff)
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Update.
2003-03-20 Ulrich Drepper <drepper@redhat.com> * include/atomic.h: Define atomic_exchange and atomic_decrement_if_positive if not already defined. Add some __builtin_expect. * sysdeps/i386/i486/bits/atomic.h: Define atomic_exchange. * sysdeps/x86_64/bits/atomic.h: Likewise. * sysdeps/ia64/bits/atomic.h: Pretty printing. Define atomic_exchange. * sysdeps/powerpc/bits/atomic.h: Pretty printing. Define atomic_exchange, atomic_exchange_and_add, and atomic_decrement_if_positive
Diffstat (limited to 'sysdeps/powerpc/bits')
-rw-r--r--sysdeps/powerpc/bits/atomic.h66
1 files changed, 58 insertions, 8 deletions
diff --git a/sysdeps/powerpc/bits/atomic.h b/sysdeps/powerpc/bits/atomic.h
index af61563..13001cb 100644
--- a/sysdeps/powerpc/bits/atomic.h
+++ b/sysdeps/powerpc/bits/atomic.h
@@ -53,11 +53,11 @@ typedef uintmax_t uatomic_max_t;
(abort (), 0)
#ifdef UP
-#define __ARCH_ACQ_INSTR ""
-#define __ARCH_REL_INSTR ""
+# define __ARCH_ACQ_INSTR ""
+# define __ARCH_REL_INSTR ""
#else
-#define __ARCH_ACQ_INSTR "isync"
-#define __ARCH_REL_INSTR "sync"
+# define __ARCH_ACQ_INSTR "isync"
+# define __ARCH_REL_INSTR "sync"
#endif
/*
@@ -86,7 +86,7 @@ typedef uintmax_t uatomic_max_t;
})
#ifdef __powerpc64__
-#define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
+# define __arch_compare_and_exchange_64_acq(mem, newval, oldval)\
({ \
unsigned long __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
@@ -103,14 +103,64 @@ typedef uintmax_t uatomic_max_t;
})
#else /* powerpc32 */
-#define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
+# define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
(abort (), 0)
#endif
+
+#define atomic_exchange(mem, value) \
+ ({ if (sizeof (*mem) != 4) \
+ abort (); \
+ int __val, __tmp; \
+ __asm __volatile (__ARCH_REL_INSTR "\n" \
+ "1: lwarx %0,0,%2\n" \
+ " stwcx. %3,0,%2\n" \
+ " bne- 1b" \
+ : "=&r" (__val), "=m" (*mem) \
+ : "r" (mem), "r" (value), "1" (*mem) \
+ : "cr0", "memory"); \
+ __val; })
+
+
+#define atomic_exchange_and_add(mem, value) \
+ ({ if (sizeof (*mem) != 4) \
+ abort (); \
+ int __val, __tmp; \
+ __asm __volatile ("1: lwarx %0,0,%3\n" \
+ " addi %1,%0,%4\n" \
+ " stwcx. %1,0,%3\n" \
+ " bne- 1b" \
+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
+ : "r" (mem), "I" (value), "2" (*mem) \
+ : "cr0"); \
+ __val; \
+ })
+
+
+/* Decrement *MEM if it is > 0, and return the old value. */
+#define atomic_decrement_if_positive(mem) \
+ ({ if (sizeof (*mem) != 4) \
+ abort (); \
+ int __val, __tmp; \
+ __asm __volatile ("1: lwarx %0,0,%3\n" \
+ " cmpwi 0,%0,0\n" \
+ " addi %1,%0,-1\n" \
+ " ble 2f\n" \
+ " stwcx. %1,0,%3\n" \
+ " bne- 1b\n" \
+ "2: " __ARCH_ACQ_INSTR \
+ : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
+ : "r" (mem), "2" (*mem) \
+ : "cr0"); \
+ __val; \
+ })
+
+
+
#define atomic_full_barrier() __asm ("sync" ::: "memory")
#ifdef __powerpc64__
-#define atomic_read_barrier() __asm ("lwsync" ::: "memory")
+# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
#else
-#define atomic_read_barrier() __asm ("sync" ::: "memory")
+# define atomic_read_barrier() __asm ("sync" ::: "memory")
#endif
#define atomic_write_barrier() __asm ("eieio" ::: "memory")