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authorUlrich Drepper <drepper@redhat.com>2003-07-22 00:14:36 +0000
committerUlrich Drepper <drepper@redhat.com>2003-07-22 00:14:36 +0000
commitb72e048f190dba7202751d8c27508f82e015ebad (patch)
treef6afe8b7897b981d99b636c5081fb45ab060f580 /sysdeps/i386
parent1a379ea0c7adae02b4cd08410a5204e8b725064d (diff)
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Update.
* sysdeps/i386/fpu/fedisblxcpt.c: Use dl_hwcap, not dl_hwcap_mask. * sysdeps/i386/fpu/feenablxcpt.c: Likewise. * sysdeps/i386/fpu/feholdexcpt.c: Likewise. * sysdeps/i386/fpu/fesetround.c: Likewise. * sysdeps/i386/fpu/ftestexcept.c: Likewise.
Diffstat (limited to 'sysdeps/i386')
-rw-r--r--sysdeps/i386/fpu/fedisblxcpt.c2
-rw-r--r--sysdeps/i386/fpu/feenablxcpt.c2
-rw-r--r--sysdeps/i386/fpu/feholdexcpt.c2
-rw-r--r--sysdeps/i386/fpu/fesetround.c2
-rw-r--r--sysdeps/i386/fpu/ftestexcept.c2
5 files changed, 5 insertions, 5 deletions
diff --git a/sysdeps/i386/fpu/fedisblxcpt.c b/sysdeps/i386/fpu/fedisblxcpt.c
index 6e337d3..ef3dd9a 100644
--- a/sysdeps/i386/fpu/fedisblxcpt.c
+++ b/sysdeps/i386/fpu/fedisblxcpt.c
@@ -39,7 +39,7 @@ fedisableexcept (int excepts)
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xnew_exc;
diff --git a/sysdeps/i386/fpu/feenablxcpt.c b/sysdeps/i386/fpu/feenablxcpt.c
index 0f841ca..a000d02 100644
--- a/sysdeps/i386/fpu/feenablxcpt.c
+++ b/sysdeps/i386/fpu/feenablxcpt.c
@@ -39,7 +39,7 @@ feenableexcept (int excepts)
__asm__ ("fldcw %0" : : "m" (*&new_exc));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xnew_exc;
diff --git a/sysdeps/i386/fpu/feholdexcpt.c b/sysdeps/i386/fpu/feholdexcpt.c
index 5d622ad..2d6cc0d 100644
--- a/sysdeps/i386/fpu/feholdexcpt.c
+++ b/sysdeps/i386/fpu/feholdexcpt.c
@@ -36,7 +36,7 @@ feholdexcept (fenv_t *envp)
__asm__ ("fldcw %0" : : "m" (*&work));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xwork;
diff --git a/sysdeps/i386/fpu/fesetround.c b/sysdeps/i386/fpu/fesetround.c
index fae74d3..fe9889f 100644
--- a/sysdeps/i386/fpu/fesetround.c
+++ b/sysdeps/i386/fpu/fesetround.c
@@ -38,7 +38,7 @@ fesetround (int round)
__asm__ ("fldcw %0" : : "m" (*&cw));
/* If the CPU supports SSE we set the MXCSR as well. */
- if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
{
unsigned int xcw;
diff --git a/sysdeps/i386/fpu/ftestexcept.c b/sysdeps/i386/fpu/ftestexcept.c
index e449571..f82b355 100644
--- a/sysdeps/i386/fpu/ftestexcept.c
+++ b/sysdeps/i386/fpu/ftestexcept.c
@@ -33,7 +33,7 @@ fetestexcept (int excepts)
__asm__ ("fnstsw %0" : "=a" (temp));
/* If the CPU supports SSE we test the MXCSR as well. */
- if ((GL(dl_hwcap_mask) & HWCAP_I386_XMM) != 0)
+ if ((GL(dl_hwcap) & HWCAP_I386_XMM) != 0)
__asm__ ("stmxcsr %0" : "=m" (*&xtemp));
return (temp | xtemp) & excepts & FE_ALL_EXCEPT;