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authorWilco Dijkstra <wilco.dijkstra@arm.com>2023-01-11 13:52:23 +0000
committerWilco Dijkstra <wilco.dijkstra@arm.com>2023-01-17 15:09:18 +0000
commit09ebd8549b2ce5a3a6c0c7c5f3e62227faf50a99 (patch)
tree622dd725d9427e8afc3af67c02bb0eff7bf48810 /sysdeps/aarch64
parent51541a229740801882490177fa178e49264b13fb (diff)
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AArch64: Improve strchrnul
Unroll the main loop, which improves performance slightly. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64')
-rw-r--r--sysdeps/aarch64/strchrnul.S12
1 files changed, 10 insertions, 2 deletions
diff --git a/sysdeps/aarch64/strchrnul.S b/sysdeps/aarch64/strchrnul.S
index 4ca1e58..aa8c9a4 100644
--- a/sysdeps/aarch64/strchrnul.S
+++ b/sysdeps/aarch64/strchrnul.S
@@ -70,14 +70,22 @@ ENTRY (__strchrnul)
.p2align 4
L(loop):
- ldr qdata, [src, 16]!
+ ldr qdata, [src, 16]
+ cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
+ cmhs vhas_chr.16b, vhas_chr.16b, vdata.16b
+ umaxp vend.16b, vhas_chr.16b, vhas_chr.16b
+ fmov tmp1, dend
+ cbnz tmp1, L(end)
+ ldr qdata, [src, 32]!
cmeq vhas_chr.16b, vdata.16b, vrepchr.16b
cmhs vhas_chr.16b, vhas_chr.16b, vdata.16b
umaxp vend.16b, vhas_chr.16b, vhas_chr.16b
fmov tmp1, dend
cbz tmp1, L(loop)
-
+ sub src, src, 16
+L(end):
shrn vend.8b, vhas_chr.8h, 4 /* 128->64 */
+ add src, src, 16
fmov tmp1, dend
#ifndef __AARCH64EB__
rbit tmp1, tmp1