diff options
author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-11-16 13:24:18 +0000 |
---|---|---|
committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-11-20 17:53:14 +0000 |
commit | a8830c928540011120ac742d632ed51d52af01df (patch) | |
tree | 3c219e1d2abfb616ebb3a512bcccabcd415dab29 /sysdeps/aarch64/fpu | |
parent | 65341f7bbea824d2ff9d37db15d8be162df42bd3 (diff) | |
download | glibc-a8830c928540011120ac742d632ed51d52af01df.zip glibc-a8830c928540011120ac742d632ed51d52af01df.tar.gz glibc-a8830c928540011120ac742d632ed51d52af01df.tar.bz2 |
aarch64: Add vector implementations of expm1 routines
May discard sign of 0 - auto tests for -0 and -0x1p-10000 updated accordingly.
Diffstat (limited to 'sysdeps/aarch64/fpu')
-rw-r--r-- | sysdeps/aarch64/fpu/Makefile | 1 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/Versions | 4 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/bits/math-vector.h | 4 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/expm1_advsimd.c | 122 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/expm1_sve.c | 99 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/expm1f_advsimd.c | 117 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/expm1f_sve.c | 99 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c | 1 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/test-double-sve-wrappers.c | 1 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | 1 | ||||
-rw-r--r-- | sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 |
11 files changed, 450 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile index c77c709..1fe4b52 100644 --- a/sysdeps/aarch64/fpu/Makefile +++ b/sysdeps/aarch64/fpu/Makefile @@ -6,6 +6,7 @@ libmvec-supported-funcs = acos \ exp \ exp10 \ exp2 \ + expm1 \ log \ log10 \ log1p \ diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions index 2543649..aaacaca 100644 --- a/sysdeps/aarch64/fpu/Versions +++ b/sysdeps/aarch64/fpu/Versions @@ -42,6 +42,10 @@ libmvec { _ZGVnN2v_exp2; _ZGVsMxv_exp2f; _ZGVsMxv_exp2; + _ZGVnN4v_expm1f; + _ZGVnN2v_expm1; + _ZGVsMxv_expm1f; + _ZGVsMxv_expm1; _ZGVnN4v_log10f; _ZGVnN2v_log10; _ZGVsMxv_log10f; diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h index 51915ce..52aad95 100644 --- a/sysdeps/aarch64/fpu/bits/math-vector.h +++ b/sysdeps/aarch64/fpu/bits/math-vector.h @@ -57,6 +57,7 @@ __vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_exp10f (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_exp2f (__f32x4_t); +__vpcs __f32x4_t _ZGVnN4v_expm1f (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_logf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_log10f (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_log1pf (__f32x4_t); @@ -72,6 +73,7 @@ __vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_exp10 (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_exp2 (__f64x2_t); +__vpcs __f64x2_t _ZGVnN2v_expm1 (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_log (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_log10 (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_log1p (__f64x2_t); @@ -92,6 +94,7 @@ __sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_exp10f (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_exp2f (__sv_f32_t, __sv_bool_t); +__sv_f32_t _ZGVsMxv_expm1f (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_logf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_log10f (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_log1pf (__sv_f32_t, __sv_bool_t); @@ -107,6 +110,7 @@ __sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_exp10 (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_exp2 (__sv_f64_t, __sv_bool_t); +__sv_f64_t _ZGVsMxv_expm1 (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_log (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_log10 (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_log1p (__sv_f64_t, __sv_bool_t); diff --git a/sysdeps/aarch64/fpu/expm1_advsimd.c b/sysdeps/aarch64/fpu/expm1_advsimd.c new file mode 100644 index 0000000..a3aed8e --- /dev/null +++ b/sysdeps/aarch64/fpu/expm1_advsimd.c @@ -0,0 +1,122 @@ +/* Double-precision AdvSIMD expm1 + + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <https://www.gnu.org/licenses/>. */ + +#include "v_math.h" +#include "poly_advsimd_f64.h" + +static const struct data +{ + float64x2_t poly[11]; + float64x2_t invln2, ln2_lo, ln2_hi, shift; + int64x2_t exponent_bias; +#if WANT_SIMD_EXCEPT + uint64x2_t thresh, tiny_bound; +#else + float64x2_t oflow_bound; +#endif +} data = { + /* Generated using fpminimax, with degree=12 in [log(2)/2, log(2)/2]. */ + .poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5), + V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10), + V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16), + V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22), + V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29) }, + .invln2 = V2 (0x1.71547652b82fep0), + .ln2_hi = V2 (0x1.62e42fefa39efp-1), + .ln2_lo = V2 (0x1.abc9e3b39803fp-56), + .shift = V2 (0x1.8p52), + .exponent_bias = V2 (0x3ff0000000000000), +#if WANT_SIMD_EXCEPT + /* asuint64(oflow_bound) - asuint64(0x1p-51), shifted left by 1 for abs + compare. */ + .thresh = V2 (0x78c56fa6d34b552), + /* asuint64(0x1p-51) << 1. */ + .tiny_bound = V2 (0x3cc0000000000000 << 1), +#else + /* Value above which expm1(x) should overflow. Absolute value of the + underflow bound is greater than this, so it catches both cases - there is + a small window where fallbacks are triggered unnecessarily. */ + .oflow_bound = V2 (0x1.62b7d369a5aa9p+9), +#endif +}; + +static float64x2_t VPCS_ATTR NOINLINE +special_case (float64x2_t x, float64x2_t y, uint64x2_t special) +{ + return v_call_f64 (expm1, x, y, special); +} + +/* Double-precision vector exp(x) - 1 function. + The maximum error observed error is 2.18 ULP: + _ZGVnN2v_expm1 (0x1.634ba0c237d7bp-2) got 0x1.a8b9ea8d66e22p-2 + want 0x1.a8b9ea8d66e2p-2. */ +float64x2_t VPCS_ATTR V_NAME_D1 (expm1) (float64x2_t x) +{ + const struct data *d = ptr_barrier (&data); + + uint64x2_t ix = vreinterpretq_u64_f64 (x); + +#if WANT_SIMD_EXCEPT + /* If fp exceptions are to be triggered correctly, fall back to scalar for + |x| < 2^-51, |x| > oflow_bound, Inf & NaN. Add ix to itself for + shift-left by 1, and compare with thresh which was left-shifted offline - + this is effectively an absolute compare. */ + uint64x2_t special + = vcgeq_u64 (vsubq_u64 (vaddq_u64 (ix, ix), d->tiny_bound), d->thresh); + if (__glibc_unlikely (v_any_u64 (special))) + x = v_zerofy_f64 (x, special); +#else + /* Large input, NaNs and Infs. */ + uint64x2_t special = vceqzq_u64 (vcaltq_f64 (x, d->oflow_bound)); +#endif + + /* Reduce argument to smaller range: + Let i = round(x / ln2) + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 + where 2^i is exact because i is an integer. */ + float64x2_t n = vsubq_f64 (vfmaq_f64 (d->shift, d->invln2, x), d->shift); + int64x2_t i = vcvtq_s64_f64 (n); + float64x2_t f = vfmsq_f64 (x, n, d->ln2_hi); + f = vfmsq_f64 (f, n, d->ln2_lo); + + /* Approximate expm1(f) using polynomial. + Taylor expansion for expm1(x) has the form: + x + ax^2 + bx^3 + cx^4 .... + So we calculate the polynomial P(f) = a + bf + cf^2 + ... + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ + float64x2_t f2 = vmulq_f64 (f, f); + float64x2_t f4 = vmulq_f64 (f2, f2); + float64x2_t f8 = vmulq_f64 (f4, f4); + float64x2_t p = vfmaq_f64 (f, f2, v_estrin_10_f64 (f, f2, f4, f8, d->poly)); + + /* Assemble the result. + expm1(x) ~= 2^i * (p + 1) - 1 + Let t = 2^i. */ + int64x2_t u = vaddq_s64 (vshlq_n_s64 (i, 52), d->exponent_bias); + float64x2_t t = vreinterpretq_f64_s64 (u); + + if (__glibc_unlikely (v_any_u64 (special))) + return special_case (vreinterpretq_f64_u64 (ix), + vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t), + special); + + /* expm1(x) ~= p * t + (t - 1). */ + return vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t); +} diff --git a/sysdeps/aarch64/fpu/expm1_sve.c b/sysdeps/aarch64/fpu/expm1_sve.c new file mode 100644 index 0000000..50646af --- /dev/null +++ b/sysdeps/aarch64/fpu/expm1_sve.c @@ -0,0 +1,99 @@ +/* Double-precision SVE expm1 + + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <https://www.gnu.org/licenses/>. */ + +#include "sv_math.h" +#include "poly_sve_f64.h" + +#define SpecialBound 0x1.62b7d369a5aa9p+9 +#define ExponentBias 0x3ff0000000000000 + +static const struct data +{ + double poly[11]; + double shift, inv_ln2, special_bound; + /* To be loaded in one quad-word. */ + double ln2_hi, ln2_lo; +} data = { + /* Generated using fpminimax. */ + .poly = { 0x1p-1, 0x1.5555555555559p-3, 0x1.555555555554bp-5, + 0x1.111111110f663p-7, 0x1.6c16c16c1b5f3p-10, 0x1.a01a01affa35dp-13, + 0x1.a01a018b4ecbbp-16, 0x1.71ddf82db5bb4p-19, 0x1.27e517fc0d54bp-22, + 0x1.af5eedae67435p-26, 0x1.1f143d060a28ap-29, }, + + .special_bound = SpecialBound, + .inv_ln2 = 0x1.71547652b82fep0, + .ln2_hi = 0x1.62e42fefa39efp-1, + .ln2_lo = 0x1.abc9e3b39803fp-56, + .shift = 0x1.8p52, +}; + +static svfloat64_t NOINLINE +special_case (svfloat64_t x, svfloat64_t y, svbool_t pg) +{ + return sv_call_f64 (expm1, x, y, pg); +} + +/* Double-precision vector exp(x) - 1 function. + The maximum error observed error is 2.18 ULP: + _ZGVsMxv_expm1(0x1.634ba0c237d7bp-2) got 0x1.a8b9ea8d66e22p-2 + want 0x1.a8b9ea8d66e2p-2. */ +svfloat64_t SV_NAME_D1 (expm1) (svfloat64_t x, svbool_t pg) +{ + const struct data *d = ptr_barrier (&data); + + /* Large, Nan/Inf. */ + svbool_t special = svnot_z (pg, svaclt (pg, x, d->special_bound)); + + /* Reduce argument to smaller range: + Let i = round(x / ln2) + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 + where 2^i is exact because i is an integer. */ + svfloat64_t shift = sv_f64 (d->shift); + svfloat64_t n = svsub_x (pg, svmla_x (pg, shift, x, d->inv_ln2), shift); + svint64_t i = svcvt_s64_x (pg, n); + svfloat64_t ln2 = svld1rq (svptrue_b64 (), &d->ln2_hi); + svfloat64_t f = svmls_lane (x, n, ln2, 0); + f = svmls_lane (f, n, ln2, 1); + + /* Approximate expm1(f) using polynomial. + Taylor expansion for expm1(x) has the form: + x + ax^2 + bx^3 + cx^4 .... + So we calculate the polynomial P(f) = a + bf + cf^2 + ... + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ + svfloat64_t f2 = svmul_x (pg, f, f); + svfloat64_t f4 = svmul_x (pg, f2, f2); + svfloat64_t f8 = svmul_x (pg, f4, f4); + svfloat64_t p + = svmla_x (pg, f, f2, sv_estrin_10_f64_x (pg, f, f2, f4, f8, d->poly)); + + /* Assemble the result. + expm1(x) ~= 2^i * (p + 1) - 1 + Let t = 2^i. */ + svint64_t u = svadd_x (pg, svlsl_x (pg, i, 52), ExponentBias); + svfloat64_t t = svreinterpret_f64 (u); + + /* expm1(x) ~= p * t + (t - 1). */ + svfloat64_t y = svmla_x (pg, svsub_x (pg, t, 1), p, t); + + if (__glibc_unlikely (svptest_any (pg, special))) + return special_case (x, y, special); + + return y; +} diff --git a/sysdeps/aarch64/fpu/expm1f_advsimd.c b/sysdeps/aarch64/fpu/expm1f_advsimd.c new file mode 100644 index 0000000..b27b750 --- /dev/null +++ b/sysdeps/aarch64/fpu/expm1f_advsimd.c @@ -0,0 +1,117 @@ +/* Single-precision AdvSIMD expm1 + + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <https://www.gnu.org/licenses/>. */ + +#include "v_math.h" +#include "poly_advsimd_f32.h" + +static const struct data +{ + float32x4_t poly[5]; + float32x4_t invln2, ln2_lo, ln2_hi, shift; + int32x4_t exponent_bias; +#if WANT_SIMD_EXCEPT + uint32x4_t thresh; +#else + float32x4_t oflow_bound; +#endif +} data = { + /* Generated using fpminimax with degree=5 in [-log(2)/2, log(2)/2]. */ + .poly = { V4 (0x1.fffffep-2), V4 (0x1.5554aep-3), V4 (0x1.555736p-5), + V4 (0x1.12287cp-7), V4 (0x1.6b55a2p-10) }, + .invln2 = V4 (0x1.715476p+0f), + .ln2_hi = V4 (0x1.62e4p-1f), + .ln2_lo = V4 (0x1.7f7d1cp-20f), + .shift = V4 (0x1.8p23f), + .exponent_bias = V4 (0x3f800000), +#if !WANT_SIMD_EXCEPT + /* Value above which expm1f(x) should overflow. Absolute value of the + underflow bound is greater than this, so it catches both cases - there is + a small window where fallbacks are triggered unnecessarily. */ + .oflow_bound = V4 (0x1.5ebc4p+6), +#else + /* asuint(oflow_bound) - asuint(0x1p-23), shifted left by 1 for absolute + compare. */ + .thresh = V4 (0x1d5ebc40), +#endif +}; + +/* asuint(0x1p-23), shifted by 1 for abs compare. */ +#define TinyBound v_u32 (0x34000000 << 1) + +static float32x4_t VPCS_ATTR NOINLINE +special_case (float32x4_t x, float32x4_t y, uint32x4_t special) +{ + return v_call_f32 (expm1f, x, y, special); +} + +/* Single-precision vector exp(x) - 1 function. + The maximum error is 1.51 ULP: + _ZGVnN4v_expm1f (0x1.8baa96p-2) got 0x1.e2fb9p-2 + want 0x1.e2fb94p-2. */ +float32x4_t VPCS_ATTR V_NAME_F1 (expm1) (float32x4_t x) +{ + const struct data *d = ptr_barrier (&data); + uint32x4_t ix = vreinterpretq_u32_f32 (x); + +#if WANT_SIMD_EXCEPT + /* If fp exceptions are to be triggered correctly, fall back to scalar for + |x| < 2^-23, |x| > oflow_bound, Inf & NaN. Add ix to itself for + shift-left by 1, and compare with thresh which was left-shifted offline - + this is effectively an absolute compare. */ + uint32x4_t special + = vcgeq_u32 (vsubq_u32 (vaddq_u32 (ix, ix), TinyBound), d->thresh); + if (__glibc_unlikely (v_any_u32 (special))) + x = v_zerofy_f32 (x, special); +#else + /* Handles very large values (+ve and -ve), +/-NaN, +/-Inf. */ + uint32x4_t special = vceqzq_u32 (vcaltq_f32 (x, d->oflow_bound)); +#endif + + /* Reduce argument to smaller range: + Let i = round(x / ln2) + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 + where 2^i is exact because i is an integer. */ + float32x4_t j = vsubq_f32 (vfmaq_f32 (d->shift, d->invln2, x), d->shift); + int32x4_t i = vcvtq_s32_f32 (j); + float32x4_t f = vfmsq_f32 (x, j, d->ln2_hi); + f = vfmsq_f32 (f, j, d->ln2_lo); + + /* Approximate expm1(f) using polynomial. + Taylor expansion for expm1(x) has the form: + x + ax^2 + bx^3 + cx^4 .... + So we calculate the polynomial P(f) = a + bf + cf^2 + ... + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ + float32x4_t p = v_horner_4_f32 (f, d->poly); + p = vfmaq_f32 (f, vmulq_f32 (f, f), p); + + /* Assemble the result. + expm1(x) ~= 2^i * (p + 1) - 1 + Let t = 2^i. */ + int32x4_t u = vaddq_s32 (vshlq_n_s32 (i, 23), d->exponent_bias); + float32x4_t t = vreinterpretq_f32_s32 (u); + + if (__glibc_unlikely (v_any_u32 (special))) + return special_case (vreinterpretq_f32_u32 (ix), + vfmaq_f32 (vsubq_f32 (t, v_f32 (1.0f)), p, t), + special); + + /* expm1(x) ~= p * t + (t - 1). */ + return vfmaq_f32 (vsubq_f32 (t, v_f32 (1.0f)), p, t); +} diff --git a/sysdeps/aarch64/fpu/expm1f_sve.c b/sysdeps/aarch64/fpu/expm1f_sve.c new file mode 100644 index 0000000..96e579e --- /dev/null +++ b/sysdeps/aarch64/fpu/expm1f_sve.c @@ -0,0 +1,99 @@ +/* Single-precision SVE expm1 + + Copyright (C) 2023 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <https://www.gnu.org/licenses/>. */ + +#include "sv_math.h" +#include "poly_sve_f32.h" + +/* Largest value of x for which expm1(x) should round to -1. */ +#define SpecialBound 0x1.5ebc4p+6f + +static const struct data +{ + /* These 4 are grouped together so they can be loaded as one quadword, then + used with _lane forms of svmla/svmls. */ + float c2, c4, ln2_hi, ln2_lo; + float c0, c1, c3, inv_ln2, special_bound, shift; +} data = { + /* Generated using fpminimax. */ + .c0 = 0x1.fffffep-2, .c1 = 0x1.5554aep-3, + .c2 = 0x1.555736p-5, .c3 = 0x1.12287cp-7, + .c4 = 0x1.6b55a2p-10, + + .special_bound = SpecialBound, .shift = 0x1.8p23f, + .inv_ln2 = 0x1.715476p+0f, .ln2_hi = 0x1.62e4p-1f, + .ln2_lo = 0x1.7f7d1cp-20f, +}; + +#define C(i) sv_f32 (d->c##i) + +static svfloat32_t NOINLINE +special_case (svfloat32_t x, svbool_t pg) +{ + return sv_call_f32 (expm1f, x, x, pg); +} + +/* Single-precision SVE exp(x) - 1. Maximum error is 1.52 ULP: + _ZGVsMxv_expm1f(0x1.8f4ebcp-2) got 0x1.e859dp-2 + want 0x1.e859d4p-2. */ +svfloat32_t SV_NAME_F1 (expm1) (svfloat32_t x, svbool_t pg) +{ + const struct data *d = ptr_barrier (&data); + + /* Large, NaN/Inf. */ + svbool_t special = svnot_z (pg, svaclt (pg, x, d->special_bound)); + + if (__glibc_unlikely (svptest_any (pg, special))) + return special_case (x, pg); + + /* This vector is reliant on layout of data - it contains constants + that can be used with _lane forms of svmla/svmls. Values are: + [ coeff_2, coeff_4, ln2_hi, ln2_lo ]. */ + svfloat32_t lane_constants = svld1rq (svptrue_b32 (), &d->c2); + + /* Reduce argument to smaller range: + Let i = round(x / ln2) + and f = x - i * ln2, then f is in [-ln2/2, ln2/2]. + exp(x) - 1 = 2^i * (expm1(f) + 1) - 1 + where 2^i is exact because i is an integer. */ + svfloat32_t j = svmla_x (pg, sv_f32 (d->shift), x, d->inv_ln2); + j = svsub_x (pg, j, d->shift); + svint32_t i = svcvt_s32_x (pg, j); + + svfloat32_t f = svmls_lane (x, j, lane_constants, 2); + f = svmls_lane (f, j, lane_constants, 3); + + /* Approximate expm1(f) using polynomial. + Taylor expansion for expm1(x) has the form: + x + ax^2 + bx^3 + cx^4 .... + So we calculate the polynomial P(f) = a + bf + cf^2 + ... + and assemble the approximation expm1(f) ~= f + f^2 * P(f). */ + svfloat32_t p12 = svmla_lane (C (1), f, lane_constants, 0); + svfloat32_t p34 = svmla_lane (C (3), f, lane_constants, 1); + svfloat32_t f2 = svmul_x (pg, f, f); + svfloat32_t p = svmla_x (pg, p12, f2, p34); + p = svmla_x (pg, C (0), f, p); + p = svmla_x (pg, f, f2, p); + + /* Assemble the result. + expm1(x) ~= 2^i * (p + 1) - 1 + Let t = 2^i. */ + svfloat32_t t = svreinterpret_f32 ( + svadd_x (pg, svreinterpret_u32 (svlsl_x (pg, i, 23)), 0x3f800000)); + return svmla_x (pg, svsub_x (pg, t, 1), p, t); +} diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c index fc9e7ae..bf49545 100644 --- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c +++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c @@ -31,6 +31,7 @@ VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos) VPCS_VECTOR_WRAPPER (exp_advsimd, _ZGVnN2v_exp) VPCS_VECTOR_WRAPPER (exp10_advsimd, _ZGVnN2v_exp10) VPCS_VECTOR_WRAPPER (exp2_advsimd, _ZGVnN2v_exp2) +VPCS_VECTOR_WRAPPER (expm1_advsimd, _ZGVnN2v_expm1) VPCS_VECTOR_WRAPPER (log_advsimd, _ZGVnN2v_log) VPCS_VECTOR_WRAPPER (log10_advsimd, _ZGVnN2v_log10) VPCS_VECTOR_WRAPPER (log1p_advsimd, _ZGVnN2v_log1p) diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c index aea589d..b5a627a 100644 --- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c +++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c @@ -50,6 +50,7 @@ SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos) SVE_VECTOR_WRAPPER (exp_sve, _ZGVsMxv_exp) SVE_VECTOR_WRAPPER (exp10_sve, _ZGVsMxv_exp10) SVE_VECTOR_WRAPPER (exp2_sve, _ZGVsMxv_exp2) +SVE_VECTOR_WRAPPER (expm1_sve, _ZGVsMxv_expm1) SVE_VECTOR_WRAPPER (log_sve, _ZGVsMxv_log) SVE_VECTOR_WRAPPER (log10_sve, _ZGVsMxv_log10) SVE_VECTOR_WRAPPER (log1p_sve, _ZGVsMxv_log1p) diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c index 446fd7f..26d9e98 100644 --- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c @@ -31,6 +31,7 @@ VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf) VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf) VPCS_VECTOR_WRAPPER (exp10f_advsimd, _ZGVnN4v_exp10f) VPCS_VECTOR_WRAPPER (exp2f_advsimd, _ZGVnN4v_exp2f) +VPCS_VECTOR_WRAPPER (expm1f_advsimd, _ZGVnN4v_expm1f) VPCS_VECTOR_WRAPPER (logf_advsimd, _ZGVnN4v_logf) VPCS_VECTOR_WRAPPER (log10f_advsimd, _ZGVnN4v_log10f) VPCS_VECTOR_WRAPPER (log1pf_advsimd, _ZGVnN4v_log1pf) diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c index ac17f60..f286ee6 100644 --- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c @@ -50,6 +50,7 @@ SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf) SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf) SVE_VECTOR_WRAPPER (exp10f_sve, _ZGVsMxv_exp10f) SVE_VECTOR_WRAPPER (exp2f_sve, _ZGVsMxv_exp2f) +SVE_VECTOR_WRAPPER (expm1f_sve, _ZGVsMxv_expm1f) SVE_VECTOR_WRAPPER (logf_sve, _ZGVsMxv_logf) SVE_VECTOR_WRAPPER (log10f_sve, _ZGVsMxv_log10f) SVE_VECTOR_WRAPPER (log1pf_sve, _ZGVsMxv_log1pf) |