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author | Steve Ellcey <sellcey@mips.com> | 2013-09-23 09:58:30 -0700 |
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committer | Steve Ellcey <sellcey@mips.com> | 2013-09-23 09:58:30 -0700 |
commit | c79fb0ed652b62eef9b42442cfc22bbc9c1e56bf (patch) | |
tree | c514e8cf3bc69e7c420df075c49d68cd528e5f3b /ports/sysdeps | |
parent | d93fa6592bd2c400f3e924bd3da94d049b8c5f5e (diff) | |
download | glibc-c79fb0ed652b62eef9b42442cfc22bbc9c1e56bf.zip glibc-c79fb0ed652b62eef9b42442cfc22bbc9c1e56bf.tar.gz glibc-c79fb0ed652b62eef9b42442cfc22bbc9c1e56bf.tar.bz2 |
2013-09-23 Steve Ellcey <sellcey@mips.com>
* sysdeps/mips/math_private.h (libc_feholdexcept_mips): New function.
(libc_feholdexcept): New macro.
(libc_feholdexceptf): New macro.
(libc_feholdexceptl): New macro.
(libc_fesetround_mips): New function.
(libc_fesetround): New macro.
(libc_fesetroundf): New macro.
(libc_fesetroundl): New macro.
(libc_feholdexcept_setround_mips): New function.
(libc_feholdexcept_setround): New macro.
(libc_feholdexcept_setroundf): New macro.
(libc_feholdexcept_setroundl): New macro.
(libc_fesetenv_mips): New function.
(libc_fesetenv): New macro.
(libc_fesetenvf): New macro.
(libc_fesetenvl): New macro.
(libc_feupdateenv_mips): New function.
(libc_feupdateenv): New macro.
(libc_feupdateenvf): New macro.
(libc_feupdateenvl): New macro.
Diffstat (limited to 'ports/sysdeps')
-rw-r--r-- | ports/sysdeps/mips/math_private.h | 108 |
1 files changed, 108 insertions, 0 deletions
diff --git a/ports/sysdeps/mips/math_private.h b/ports/sysdeps/mips/math_private.h index 6b99957..4f029b0 100644 --- a/ports/sysdeps/mips/math_private.h +++ b/ports/sysdeps/mips/math_private.h @@ -26,6 +26,114 @@ # define HIGH_ORDER_BIT_IS_SET_FOR_SNAN #endif +/* Inline functions to speed up the math library implementation. The + default versions of these routines are in generic/math_private.h + and call fesetround, feholdexcept, etc. These routines use inlined + code instead. */ + +#ifdef __mips_hard_float + +# include <fenv.h> +# include <fenv_libc.h> +# include <fpu_control.h> + +static __always_inline void +libc_feholdexcept_mips (fenv_t *envp) +{ + fpu_control_t cw; + + /* Save the current state. */ + _FPU_GETCW (cw); + envp->__fp_control_register = cw; + + /* Clear all exception enable bits and flags. */ + cw &= ~(_FPU_MASK_V|_FPU_MASK_Z|_FPU_MASK_O|_FPU_MASK_U|_FPU_MASK_I|FE_ALL_EXCEPT); + _FPU_SETCW (cw); +} +# define libc_feholdexcept libc_feholdexcept_mips +# define libc_feholdexceptf libc_feholdexcept_mips +# define libc_feholdexceptl libc_feholdexcept_mips + +static __always_inline void +libc_fesetround_mips (int round) +{ + fpu_control_t cw; + + /* Get current state. */ + _FPU_GETCW (cw); + + /* Set rounding bits. */ + cw &= ~_FPU_RC_MASK; + cw |= round; + + /* Set new state. */ + _FPU_SETCW (cw); +} +# define libc_fesetround libc_fesetround_mips +# define libc_fesetroundf libc_fesetround_mips +# define libc_fesetroundl libc_fesetround_mips + +static __always_inline void +libc_feholdexcept_setround_mips (fenv_t *envp, int round) +{ + fpu_control_t cw; + + /* Save the current state. */ + _FPU_GETCW (cw); + envp->__fp_control_register = cw; + + /* Clear all exception enable bits and flags. */ + cw &= ~(_FPU_MASK_V|_FPU_MASK_Z|_FPU_MASK_O|_FPU_MASK_U|_FPU_MASK_I|FE_ALL_EXCEPT); + + /* Set rounding bits. */ + cw &= ~_FPU_RC_MASK; + cw |= round; + + /* Set new state. */ + _FPU_SETCW (cw); +} +# define libc_feholdexcept_setround libc_feholdexcept_setround_mips +# define libc_feholdexcept_setroundf libc_feholdexcept_setround_mips +# define libc_feholdexcept_setroundl libc_feholdexcept_setround_mips + +static __always_inline void +libc_fesetenv_mips (fenv_t *envp) +{ + fpu_control_t cw; + + /* Read current state to flush fpu pipeline. */ + _FPU_GETCW (cw); + + _FPU_SETCW (envp->__fp_control_register); +} +# define libc_fesetenv libc_fesetenv_mips +# define libc_fesetenvf libc_fesetenv_mips +# define libc_fesetenvl libc_fesetenv_mips + +static __always_inline void +libc_feupdateenv_mips (fenv_t *envp) +{ + int temp; + + /* Save current exceptions. */ + _FPU_GETCW (temp); + + /* Set flag bits (which are accumulative), and *also* set the + cause bits. The setting of the cause bits is what actually causes + the hardware to generate the exception, if the corresponding enable + bit is set as well. */ + temp &= FE_ALL_EXCEPT; + temp |= envp->__fp_control_register | (temp << CAUSE_SHIFT); + + /* Set new state. */ + _FPU_SETCW (temp); +} +# define libc_feupdateenv libc_feupdateenv_mips +# define libc_feupdateenvf libc_feupdateenv_mips +# define libc_feupdateenvl libc_feupdateenv_mips + +#endif + #include_next <math_private.h> #endif |