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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2013-08-22 17:50:20 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@codesourcery.com> | 2013-08-22 17:55:17 +0100 |
| commit | b72ca61b71abd3e2d5b6cdb0680d7179f95be222 (patch) | |
| tree | 79913c2c6a952e2eda419b7d0766df4c13b2f48b /ports/sysdeps/mips | |
| parent | d1141ff6c875bc53c5ef6cd62b1bbfe91bdccd21 (diff) | |
| download | glibc-b72ca61b71abd3e2d5b6cdb0680d7179f95be222.zip glibc-b72ca61b71abd3e2d5b6cdb0680d7179f95be222.tar.gz glibc-b72ca61b71abd3e2d5b6cdb0680d7179f95be222.tar.bz2 | |
MIPS: Correct the handling of reserved FCSR bits
Reserved bits in the Floating-Point Control and Status Register (FCSR)
should not be implicitly cleared by fedisableexcept or feenableexcept,
there is no reason to. Among these are the 8 condition codes and one of
the two bits reserved for architecture implementers (bits #22 & #21).
As to the latter, there is no reason to treat any of them as reserved
either, they should be user controllable and settable via __fpu_control
override as the user sees fit. For example in processors implemented by
MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to
change the treatment of denormalised operands and tiny results: bit #22
is Flush Override (FO) and bit #21 is Flush to Nearest (FN). They cause
non-IEEE-compliant behaviour, but some programs may have a use for such
modes of operation; the library should not obstruct such use just as it
does not for the architectural Flush to Zero (FS) bit (bit #24).
Therefore the change adjusts the reserved mask accordingly and also
documents the distinction between bits 22:21 and 20:18.
Diffstat (limited to 'ports/sysdeps/mips')
| -rw-r--r-- | ports/sysdeps/mips/fpu/fedisblxcpt.c | 1 | ||||
| -rw-r--r-- | ports/sysdeps/mips/fpu/feenablxcpt.c | 1 | ||||
| -rw-r--r-- | ports/sysdeps/mips/fpu_control.h | 5 |
3 files changed, 3 insertions, 4 deletions
diff --git a/ports/sysdeps/mips/fpu/fedisblxcpt.c b/ports/sysdeps/mips/fpu/fedisblxcpt.c index 1db197f..7498c0c 100644 --- a/ports/sysdeps/mips/fpu/fedisblxcpt.c +++ b/ports/sysdeps/mips/fpu/fedisblxcpt.c @@ -34,7 +34,6 @@ fedisableexcept (int excepts) excepts &= FE_ALL_EXCEPT; new_exc &= ~(excepts << ENABLE_SHIFT); - new_exc &= ~_FPU_RESERVED; _FPU_SETCW (new_exc); return old_exc; diff --git a/ports/sysdeps/mips/fpu/feenablxcpt.c b/ports/sysdeps/mips/fpu/feenablxcpt.c index 2a3a076..bca8e3d 100644 --- a/ports/sysdeps/mips/fpu/feenablxcpt.c +++ b/ports/sysdeps/mips/fpu/feenablxcpt.c @@ -34,7 +34,6 @@ feenableexcept (int excepts) excepts &= FE_ALL_EXCEPT; new_exc |= excepts << ENABLE_SHIFT; - new_exc &= ~_FPU_RESERVED; _FPU_SETCW (new_exc); return old_exc; diff --git a/ports/sysdeps/mips/fpu_control.h b/ports/sysdeps/mips/fpu_control.h index 6aecb3b..770cbb3 100644 --- a/ports/sysdeps/mips/fpu_control.h +++ b/ports/sysdeps/mips/fpu_control.h @@ -28,7 +28,8 @@ * causing unimplemented operation exception. This bit is only * available for MIPS III and newer. * 23 -> Condition bit - * 22-18 -> reserved (read as 0, write with 0) + * 22-21 -> reserved for architecture implementers + * 20-18 -> reserved (read as 0, write with 0) * 17 -> cause bit for unimplemented operation * 16 -> cause bit for invalid exception * 15 -> cause bit for division by zero exception @@ -84,7 +85,7 @@ extern fpu_control_t __fpu_control; #define _FPU_RC_UP 0x2 #define _FPU_RC_DOWN 0x3 -#define _FPU_RESERVED 0xfebc0000 /* Reserved bits in cw */ +#define _FPU_RESERVED 0xfe9c0000 /* Reserved bits in cw */ /* The fdlibm code requires strict IEEE double precision arithmetic, |