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| author | Noah Goldstein <goldstein.w.n@gmail.com> | 2023-09-20 15:44:50 -0500 |
|---|---|---|
| committer | Noah Goldstein <goldstein.w.n@gmail.com> | 2023-09-29 14:18:42 -0500 |
| commit | d90b43a4ed475dac5b0cd6e01ceb35c7b0f7f2ff (patch) | |
| tree | 0015cc47ecb9affe00f1d8afbebf4a5c16d20e25 /nptl/tst-tls5mod.c | |
| parent | 5f913506f4bf4785f9cf2c2ac8d17dc9f877ff17 (diff) | |
| download | glibc-d90b43a4ed475dac5b0cd6e01ceb35c7b0f7f2ff.zip glibc-d90b43a4ed475dac5b0cd6e01ceb35c7b0f7f2ff.tar.gz glibc-d90b43a4ed475dac5b0cd6e01ceb35c7b0f7f2ff.tar.bz2 | |
x86: Add support for AVX10 preset and vec size in cpu-features
This commit add support for the new AVX10 cpu features:
https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf
We add checks for:
- `AVX10`: Check if AVX10 is present.
- `AVX10_{X,Y,Z}MM`: Check if a given vec class has AVX10 support.
`make check` passes and cpuid output was checked against GNR/DMR on an
emulator.
Diffstat (limited to 'nptl/tst-tls5mod.c')
0 files changed, 0 insertions, 0 deletions