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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2020-07-17 14:09:36 +0100 |
|---|---|---|
| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2020-07-17 15:07:23 +0100 |
| commit | f46ef33ad134bec7ac992f28ee4b8b0614590e3e (patch) | |
| tree | f34fe31172e393172c15b2bb189382ad9c0b17e2 /math/test-fexcept.c | |
| parent | 76b8442db51a8976de19934638a42532a3af607f (diff) | |
| download | glibc-f46ef33ad134bec7ac992f28ee4b8b0614590e3e.zip glibc-f46ef33ad134bec7ac992f28ee4b8b0614590e3e.tar.gz glibc-f46ef33ad134bec7ac992f28ee4b8b0614590e3e.tar.bz2 | |
AArch64: Improve strlen_asimd performance (bug 25824)
Optimize strlen using a mix of scalar and SIMD code. On modern micro
architectures large strings are 2.6 times faster than existing
strlen_asimd and 35% faster than the new MTE version of strlen.
On a random strlen benchmark using small sizes the speedup is 7% vs
strlen_asimd and 40% vs the MTE strlen. This fixes the main strlen
regressions on Cortex-A53 and other cores with a simple Neon unit.
Rename __strlen_generic to __strlen_mte, and select strlen_asimd when
MTE is not enabled (this is waiting on support for a HWCAP_MTE bit).
This fixes big-endian bug 25824. Passes GLIBC regression tests.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'math/test-fexcept.c')
0 files changed, 0 insertions, 0 deletions