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author | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-13 01:59:12 -0800 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2018-01-25 10:06:19 -0800 |
commit | fb58aac5fe5d6198b84ce43e7c53b2830b1b332c (patch) | |
tree | c03dcc059c0aca4e2e44a7d079711661ada382bb /elf | |
parent | 128c43a2d6308668032b285ca08228bebf26e74e (diff) | |
download | glibc-fb58aac5fe5d6198b84ce43e7c53b2830b1b332c.zip glibc-fb58aac5fe5d6198b84ce43e7c53b2830b1b332c.tar.gz glibc-fb58aac5fe5d6198b84ce43e7c53b2830b1b332c.tar.bz2 |
Add support for the RISC-V-specific ELF flags
The RISC-V port defines ELF flags that enforce compatibility between
various objects. This adds the shared support necessary for these
flags.
2018-01-25 Palmer Dabbelt <palmer@sifive.com>
* elf/cache.c (print_entry): Add FLAG_RISCV_FLOAT_ABI_SOFT and
FLAG_RISCV_FLOAT_ABI_DOUBLE.
* elf/elf.h (EF_RISCV_RVC): New define.
(EF_RISCV_FLOAT_ABI): Likewise.
(EF_RISCV_FLOAT_ABI_SOFT): Likewise.
(EF_RISCV_FLOAT_ABI_SINGLE): Likewise.
(EF_RISCV_FLOAT_ABI_DOUBLE): Likewise.
(EF_RISCV_FLOAT_ABI_QUAD): Likewise.
* sysdeps/generic/ldconfig.h (FLAG_RISCV_FLOAT_ABI_SOFT): New
define.
(FLAG_RISCV_FLOAT_ABI_DOUBLE): Likewise.
Diffstat (limited to 'elf')
-rw-r--r-- | elf/cache.c | 6 | ||||
-rw-r--r-- | elf/elf.h | 8 |
2 files changed, 14 insertions, 0 deletions
diff --git a/elf/cache.c b/elf/cache.c index 1ec6ab3..c2c010f 100644 --- a/elf/cache.c +++ b/elf/cache.c @@ -114,6 +114,12 @@ print_entry (const char *lib, int flag, unsigned int osversion, case FLAG_MIPS64_LIBN64_NAN2008: fputs (",64bit,nan2008", stdout); break; + case FLAG_RISCV_FLOAT_ABI_SOFT: + fputs (",soft-float", stdout); + break; + case FLAG_RISCV_FLOAT_ABI_DOUBLE: + fputs (",double-float", stdout); + break; case 0: break; default: @@ -3766,6 +3766,14 @@ enum #define R_TILEGX_NUM 130 +/* RISC-V ELF Flags */ +#define EF_RISCV_RVC 0x0001 +#define EF_RISCV_FLOAT_ABI 0x0006 +#define EF_RISCV_FLOAT_ABI_SOFT 0x0000 +#define EF_RISCV_FLOAT_ABI_SINGLE 0x0002 +#define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 +#define EF_RISCV_FLOAT_ABI_QUAD 0x0006 + /* RISC-V relocations. */ #define R_RISCV_NONE 0 #define R_RISCV_32 1 |