aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat

The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
ctr_el0 register, which tells us the minimum observable cache line
size by userspace.  This typically is the same as the L1 cache line
size, but that may not always be true.  It could be a higher level
cache line size as long as cache cleaning and invalidation work
correctly with that line size in userspace.  The falkor core for
example reports the L2 line size as the dcache line size in CTR_EL0
while also reporting the correct L1 dcache line size via CCSIDR_EL1.

	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.

Reviewed-by: Rical Jasan <ricaljasan@pacific.net>
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/ChangeLog b/ChangeLog
index 8904437..b756f97 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,8 @@
 2017-10-23  Siddhesh Poyarekar  <siddhesh@sourceware.org>
 
+	* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
+	_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.
+
 	* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
 	_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
 	_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,