diff options
| author | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:44:03 +0000 |
|---|---|---|
| committer | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:44:03 +0000 |
| commit | 9c84384cc18ff589233628c193953ca8d7a39f5c (patch) | |
| tree | 95d1f5aee409b208db7545d678012eeae9559fae | |
| parent | 5556231db2301917cd14a7450de4eba2368c9763 (diff) | |
| download | glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.zip glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.tar.gz glibc-9c84384cc18ff589233628c193953ca8d7a39f5c.tar.bz2 | |
Remove trailing whitespace.
192 files changed, 1186 insertions, 992 deletions
@@ -1,3 +1,197 @@ +2013-06-05 Joseph Myers <joseph@codesourcery.com> + + * crypt/speeds.c: Remove trailing whitespace. + * dlfcn/default.c: Likewise. + * elf/ifuncdep2.c: Likewise. + * elf/ifuncmain1.c: Likewise. + * elf/ifuncmain1vis.c: Likewise. + * elf/testobj.h: Likewise. + * elf/tst-stackguard1.c: Likewise. + * gmon/sys/gmon.h: Likewise. + * hurd/hurdmsg.c: Likewise. + * hurd/new-fd.c: Likewise. + * hurd/ports-get.c: Likewise. + * iconvdata/ibm1008_420.c: Likewise. + * inet/tst-getni1.c: Likewise. + * inet/tst-getni2.c: Likewise. + * libio/ioungetc.c: Likewise. + * libio/wfiledoalloc.c: Likewise. + * manual/libm-err-tab.pl: Likewise. + * math/w_dremf.c: Likewise. + * misc/ftruncate.c: Likewise. + * posix/bug-glob2.c: Likewise. + * posix/tst-pcre.c: Likewise. + * posix/wait4.c: Likewise. + * resolv/README: Likewise. + * resolv/res_debug.h: Likewise. + * resolv/tst-inet_ntop.c: Likewise. + * setjmp/bug269-setjmp.c: Likewise. + * soft-fp/extended.h: Likewise. + * soft-fp/op-1.h: Likewise. + * soft-fp/op-2.h: Likewise. + * soft-fp/op-4.h: Likewise. + * soft-fp/op-8.h: Likewise. + * soft-fp/testit.c: Likewise. + * stdio-common/bug16.c: Likewise. + * stdlib/random.c: Likewise. + * sunrpc/rpcsvc/rquota.x: Likewise. + * sysdeps/ieee754/dbl-64/powtwo.tbl: Likewise. + * sysdeps/ieee754/flt-32/k_cosf.c: Likewise. + * sysdeps/ieee754/flt-32/k_rem_pio2f.c: Likewise. + * sysdeps/ieee754/flt-32/k_sinf.c: Likewise. + * sysdeps/ieee754/flt-32/k_tanf.c: Likewise. + * sysdeps/ieee754/flt-32/s_atanf.c: Likewise. + * sysdeps/ieee754/flt-32/s_copysignf.c: Likewise. + * sysdeps/ieee754/flt-32/s_erff.c: Likewise. + * sysdeps/ieee754/flt-32/s_fabsf.c: Likewise. + * sysdeps/ieee754/flt-32/s_frexpf.c: Likewise. + * sysdeps/ieee754/flt-32/s_logbf.c: Likewise. + * sysdeps/ieee754/ldbl-128/e_rem_pio2l.c: Likewise. + * sysdeps/ieee754/ldbl-128/k_tanl.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_atanl.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_erfl.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_expm1l.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_log1pl.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_nexttowardf.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_remquol.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_scalblnl.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_scalbnl.c: Likewise. + * sysdeps/ieee754/ldbl-128/s_tanl.c: Likewise. + * sysdeps/ieee754/ldbl-128/t_sincosl.c: Likewise. + * sysdeps/ieee754/ldbl-128ibm/k_cosl.c: Likewise. + * sysdeps/ieee754/ldbl-128ibm/k_sincosl.c: Likewise. + * sysdeps/ieee754/ldbl-128ibm/k_sinl.c: Likewise. + * sysdeps/ieee754/ldbl-128ibm/math_ldbl.h: Likewise. + * sysdeps/ieee754/ldbl-128ibm/s_nextafterl.c: Likewise. + * sysdeps/ieee754/ldbl-96/s_erfl.c: Likewise. + * sysdeps/ieee754/s_lib_version.c: Likewise. + * sysdeps/mach/hurd/check_fds.c: Likewise. + * sysdeps/mach/hurd/getsockname.c: Likewise. + * sysdeps/mach/hurd/net/if_ppp.h: Likewise. + * sysdeps/mach/hurd/recvfrom.c: Likewise. + * sysdeps/powerpc/bits/link.h: Likewise. + * sysdeps/powerpc/dl-procinfo.c: Likewise. + * sysdeps/powerpc/fpu/feholdexcpt.c: Likewise. + * sysdeps/powerpc/fpu/fenv_const.c: Likewise. + * sysdeps/powerpc/fpu/fesetenv.c: Likewise. + * sysdeps/powerpc/fpu/feupdateenv.c: Likewise. + * sysdeps/powerpc/fpu/s_rintf.c: Likewise. + * sysdeps/powerpc/fpu/t_sqrt.c: Likewise. + * sysdeps/powerpc/powerpc32/bits/atomic.h: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_floor.S: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_floorf.S: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_isnan.S: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_lround.S: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_round.S: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_roundf.S: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_trunc.S: Likewise. + * sysdeps/powerpc/powerpc32/fpu/s_truncf.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/fpu/s_llround.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/hp-timing.c: Likewise. + * sysdeps/powerpc/powerpc32/power4/memcmp.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/memset.S: Likewise. + * sysdeps/powerpc/powerpc32/power4/wordcopy.c: Likewise. + * sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S: Likewise. + * sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S: Likewise. + * sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S: Likewise. + * sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S: Likewise. + * sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S: Likewise. + * sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S: Likewise. + * sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S: Likewise. + * sysdeps/powerpc/powerpc32/power6/memcpy.S: Likewise. + * sysdeps/powerpc/powerpc32/power6/wordcopy.c: Likewise. + * sysdeps/powerpc/powerpc32/power6x/fpu/s_lround.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_ceill.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_floor.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_floorf.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_isnan.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_llrint.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_llrintf.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_llround.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_llroundf.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_round.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_roundf.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_roundl.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_trunc.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_truncf.S: Likewise. + * sysdeps/powerpc/powerpc64/fpu/s_truncl.S: Likewise. + * sysdeps/powerpc/powerpc64/hp-timing.c: Likewise. + * sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c: Likewise. + * sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c: Likewise. + * sysdeps/powerpc/powerpc64/power4/memcmp.S: Likewise. + * sysdeps/powerpc/powerpc64/power4/memcpy.S: Likewise. + * sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S: Likewise. + * sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S: Likewise. + * sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S: Likewise. + * sysdeps/powerpc/powerpc64/power6/memcpy.S: Likewise. + * sysdeps/powerpc/powerpc64/power6/wordcopy.c: Likewise. + * sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S: Likewise. + * sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S: Likewise. + * sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S: Likewise. + * sysdeps/powerpc/powerpc64/strlen.S: Likewise. + * sysdeps/powerpc/powerpc64/strncmp.S: Likewise. + * sysdeps/powerpc/sysdep.h: Likewise. + * sysdeps/s390/s390-64/s390x-mcount.S: Likewise. + * sysdeps/s390/s390-64/sub_n.S: Likewise. + * sysdeps/sh/dl-trampoline.S: Likewise. + * sysdeps/sh/memset.S: Likewise. + * sysdeps/sh/sh4/fpu/fclrexcpt.c: Likewise. + * sysdeps/sh/strlen.S: Likewise. + * sysdeps/sparc/sparc32/dl-trampoline.S: Likewise. + * sysdeps/sparc/sparc32/dotmul.S: Likewise. + * sysdeps/sparc/sparc32/memcpy.S: Likewise. + * sysdeps/sparc/sparc32/rem.S: Likewise. + * sysdeps/sparc/sparc32/sdiv.S: Likewise. + * sysdeps/sparc/sparc32/soft-fp/q_neg.c: Likewise. + * sysdeps/sparc/sparc32/strchr.S: Likewise. + * sysdeps/sparc/sparc32/udiv.S: Likewise. + * sysdeps/sparc/sparc32/urem.S: Likewise. + * sysdeps/sparc/sparc64/add_n.S: Likewise. + * sysdeps/sparc/sparc64/memcpy.S: Likewise. + * sysdeps/sparc/sparc64/rawmemchr.S: Likewise. + * sysdeps/sparc/sparc64/soft-fp/s_frexpl.c: Likewise. + * sysdeps/sparc/sparc64/soft-fp/sfp-machine.h: Likewise. + * sysdeps/sparc/sparc64/stpncpy.S: Likewise. + * sysdeps/sparc/sparc64/strncmp.S: Likewise. + * sysdeps/sparc/sparc64/strncpy.S: Likewise. + * sysdeps/unix/bsd/times.c: Likewise. + * sysdeps/unix/sysv/linux/a.out.h: Likewise. + * sysdeps/unix/sysv/linux/net/if_ppp.h: Likewise. + * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S: Likewise. + * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S: Likewise. + * sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions: Likewise. + * sysdeps/unix/sysv/linux/powerpc/sys/procfs.h: Likewise. + * sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-32/clone.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-32/getcontext.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-32/posix_fadvise64.c: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-32/setcontext.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-32/swapcontext.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-64/mmap.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-64/register-dump.h: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-64/setcontext.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-64/socket.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-64/swapcontext.S: Likewise. + * sysdeps/unix/sysv/linux/s390/s390-64/syscall.S: Likewise. + * sysdeps/unix/sysv/linux/scsi/scsi_ioctl.h: Likewise. + * sysdeps/unix/sysv/linux/sh/brk.c: Likewise. + * sysdeps/unix/sysv/linux/sh/clone.S: Likewise. + * sysdeps/unix/sysv/linux/sh/sh3/getcontext.S: Likewise. + * sysdeps/unix/sysv/linux/sh/sh3/register-dump.h: Likewise. + * sysdeps/unix/sysv/linux/sh/sh3/setcontext.S: Likewise. + * sysdeps/unix/sysv/linux/sh/sh3/swapcontext.S: Likewise. + * sysdeps/unix/sysv/linux/sh/vfork.S: Likewise. + * sysdeps/unix/sysv/linux/sparc/a.out.h: Likewise. + * sysdeps/unix/sysv/linux/sparc/sparc64/brk.S: Likewise. + * sysdeps/unix/sysv/linux/sys/personality.h: Likewise. + * sysdeps/x86_64/fpu/s_ceill.S: Likewise. + * sysdeps/x86_64/fpu/s_llrintl.S: Likewise. + * sysdeps/x86_64/strcspn.S: Likewise. + 2013-06-05 Ryan S. Arnold <rsa@linux.vnet.ibm.com> * locale/C-translit.h: Revert #include <stdint.h> because this is a diff --git a/crypt/speeds.c b/crypt/speeds.c index 7362391..6043eab 100644 --- a/crypt/speeds.c +++ b/crypt/speeds.c @@ -12,13 +12,13 @@ #include <stdio.h> #ifndef SIGVTALRM -/* +/* * patch from chip@chinacat.unicom.com (Chip Rosenthal): * you may enable it if your system does not include * a setitimer() function. You'll have to ensure the * existence a environment variable: HZ giving how many * ticks goes per second. - * If not existing in your default environment 50, 60 + * If not existing in your default environment 50, 60 * or even 100 may be the right value. Perhaps you should * then use 'time ./ufc 10000' instead of guessing. */ diff --git a/dlfcn/default.c b/dlfcn/default.c index eeed5a9..612ab79 100644 --- a/dlfcn/default.c +++ b/dlfcn/default.c @@ -14,7 +14,7 @@ main (int argc, char *argv[]) void *p; int result = 0; Dl_info info; - + dladdr(main, &info); if (info.dli_fname == NULL) { @@ -28,7 +28,7 @@ main (int argc, char *argv[]) } else printf ("%s: dladdr returned correct dli_fname\n", __FILE__); - + /* Find function `main'. */ p = dlsym (RTLD_DEFAULT, "main"); if (p == NULL) diff --git a/elf/ifuncdep2.c b/elf/ifuncdep2.c index 758bae1..99d1926 100644 --- a/elf/ifuncdep2.c +++ b/elf/ifuncdep2.c @@ -17,7 +17,7 @@ minus_one (void) } static int -zero (void) +zero (void) { return 0; } @@ -25,7 +25,7 @@ zero (void) void * foo1_ifunc (void) __asm__ ("foo1"); __asm__(".type foo1, %gnu_indirect_function"); -void * +void * foo1_ifunc (void) { return ifunc_sel (one, minus_one, zero); @@ -34,7 +34,7 @@ foo1_ifunc (void) void * foo2_ifunc (void) __asm__ ("foo2"); __asm__(".type foo2, %gnu_indirect_function"); -void * +void * foo2_ifunc (void) { return ifunc_sel (minus_one, one, zero); @@ -43,7 +43,7 @@ foo2_ifunc (void) void * foo3_ifunc (void) __asm__ ("foo3"); __asm__(".type foo3, %gnu_indirect_function"); -void * +void * foo3_ifunc (void) { return ifunc_sel (one, zero, minus_one); diff --git a/elf/ifuncmain1.c b/elf/ifuncmain1.c index cc1e5ec..747fc02 100644 --- a/elf/ifuncmain1.c +++ b/elf/ifuncmain1.c @@ -29,7 +29,7 @@ int main (void) { foo_p p; - + if (foo_ptr != foo) abort (); if (foo () != -1) diff --git a/elf/ifuncmain1vis.c b/elf/ifuncmain1vis.c index 81cd122..d35e2f8 100644 --- a/elf/ifuncmain1vis.c +++ b/elf/ifuncmain1vis.c @@ -50,7 +50,7 @@ int main (void) { foo_p p; - + if (foo_ptr != foo) abort (); if ((*foo_ptr) () != -30) diff --git a/elf/testobj.h b/elf/testobj.h index 12f18ef..1707ae3 100644 --- a/elf/testobj.h +++ b/elf/testobj.h @@ -15,14 +15,14 @@ extern int obj3func1 (int); extern int obj3func2 (int); extern int obj4func1 (int); - + extern int obj4func2 (int); - + extern int obj5func1 (int); - + extern int obj5func2 (int); - + extern int obj6func1 (int); - + extern int obj6func2 (int); diff --git a/elf/tst-stackguard1.c b/elf/tst-stackguard1.c index fba60bd..2caa4a7 100644 --- a/elf/tst-stackguard1.c +++ b/elf/tst-stackguard1.c @@ -160,7 +160,7 @@ do_test (void) the 16 runs, something is very wrong. */ int ndifferences = 0; int ndefaults = 0; - for (i = 0; i < N; ++i) + for (i = 0; i < N; ++i) { if (child_stack_chk_guards[i] != child_stack_chk_guards[i+1]) ndifferences++; diff --git a/gmon/sys/gmon.h b/gmon/sys/gmon.h index c02f831..5b430ab 100644 --- a/gmon/sys/gmon.h +++ b/gmon/sys/gmon.h @@ -119,10 +119,10 @@ extern struct __bb *__bb_head; */ #define ARCINDEX u_long -/* +/* * Maximum number of arcs we want to allow. - * Used to be max representable value of ARCINDEX minus 2, but now - * that ARCINDEX is a long, that's too large; we don't really want + * Used to be max representable value of ARCINDEX minus 2, but now + * that ARCINDEX is a long, that's too large; we don't really want * to allow a 48 gigabyte table. * The old value of 1<<16 wasn't high enough in practice for large C++ * programs; will 1<<20 be adequate for long? FIXME diff --git a/hurd/hurdmsg.c b/hurd/hurdmsg.c index b4b7161..6e350ee 100644 --- a/hurd/hurdmsg.c +++ b/hurd/hurdmsg.c @@ -324,7 +324,7 @@ _S_msg_get_env_variable (mach_port_t msgport, valuelen = strlen (value); if (valuelen > *datalen) { - if (err = __vm_allocate (__mach_task_self (), + if (err = __vm_allocate (__mach_task_self (), (vm_address_t *) data, valuelen, 1)) return err; } diff --git a/hurd/new-fd.c b/hurd/new-fd.c index e522056..32c7252 100644 --- a/hurd/new-fd.c +++ b/hurd/new-fd.c @@ -32,7 +32,7 @@ _hurd_new_fd (io_t port, io_t ctty) /* Initialize the port cells. */ _hurd_port_init (&d->port, port); _hurd_port_init (&d->ctty, ctty); - + /* And the fcntl flags. */ d->flags = 0; } diff --git a/hurd/ports-get.c b/hurd/ports-get.c index 7d6be6e..a4495a6 100644 --- a/hurd/ports-get.c +++ b/hurd/ports-get.c @@ -37,7 +37,7 @@ _hurd_ports_get (unsigned int which, mach_port_t *result) return EINVAL; if (which >= INIT_PORT_MAX || _hurd_ports_getters[which] == NULL) return HURD_PORT_USE (&_hurd_ports[which], - (*result = port) == MACH_PORT_NULL ? 0 + (*result = port) == MACH_PORT_NULL ? 0 : __mach_port_mod_refs (__mach_task_self (), port, MACH_PORT_RIGHT_SEND, +1)); diff --git a/iconvdata/ibm1008_420.c b/iconvdata/ibm1008_420.c index 724b745..621c1d0 100644 --- a/iconvdata/ibm1008_420.c +++ b/iconvdata/ibm1008_420.c @@ -23,138 +23,138 @@ static const char __from_ibm1008_to_ibm420[256] = { - [0x00] = 0x00, [0x01] = 0x01, [0x02] = 0x02, [0x03] = 0x03, - [0x04] = 0x37, [0x05] = 0x2D, [0x06] = 0x2E, [0x07] = 0x2F, - [0x08] = 0x16, [0x09] = 0x05, [0x0A] = 0x25, [0x0B] = 0x0B, - [0x0C] = 0x0C, [0x0D] = 0x0D, [0x0E] = 0x0E, [0x0F] = 0x0F, - [0x10] = 0x10, [0x11] = 0x11, [0x12] = 0x12, [0x13] = 0x13, - [0x14] = 0x3C, [0x15] = 0x3D, [0x16] = 0x32, [0x17] = 0x26, - [0x18] = 0x18, [0x19] = 0x19, [0x1A] = 0x3F, [0x1B] = 0x27, - [0x1C] = 0x1C, [0x1D] = 0x1D, [0x1E] = 0x1E, [0x1F] = 0x1F, - [0x20] = 0x40, [0x21] = 0x5A, [0x22] = 0x7F, [0x23] = 0x7B, - [0x24] = 0x5B, [0x25] = 0x6C, [0x26] = 0x50, [0x27] = 0x7D, - [0x28] = 0x4D, [0x29] = 0x5D, [0x2A] = 0x5C, [0x2B] = 0x4E, - [0x2C] = 0x6B, [0x2D] = 0x60, [0x2E] = 0x4B, [0x2F] = 0x61, - [0x30] = 0xF0, [0x31] = 0xF1, [0x32] = 0xF2, [0x33] = 0xF3, - [0x34] = 0xF4, [0x35] = 0xF5, [0x36] = 0xF6, [0x37] = 0xF7, - [0x38] = 0xF8, [0x39] = 0xF9, [0x3A] = 0x7A, [0x3B] = 0x5E, - [0x3C] = 0x4C, [0x3D] = 0x7E, [0x3E] = 0x6E, [0x3F] = 0x6F, - [0x40] = 0x7C, [0x41] = 0xC1, [0x42] = 0xC2, [0x43] = 0xC3, - [0x44] = 0xC4, [0x45] = 0xC5, [0x46] = 0xC6, [0x47] = 0xC7, - [0x48] = 0xC8, [0x49] = 0xC9, [0x4A] = 0xD1, [0x4B] = 0xD2, - [0x4C] = 0xD3, [0x4D] = 0xD4, [0x4E] = 0xD5, [0x4F] = 0xD6, - [0x50] = 0xD7, [0x51] = 0xD8, [0x52] = 0xD9, [0x53] = 0xE2, - [0x54] = 0xE3, [0x55] = 0xE4, [0x56] = 0xE5, [0x57] = 0xE6, - [0x58] = 0xE7, [0x59] = 0xE8, [0x5A] = 0xE9, [0x5B] = 0x53, - [0x5C] = 0x54, [0x5D] = 0xB6, [0x5E] = 0xB7, [0x5F] = 0x6D, - [0x60] = 0xCC, [0x61] = 0x81, [0x62] = 0x82, [0x63] = 0x83, - [0x64] = 0x84, [0x65] = 0x85, [0x66] = 0x86, [0x67] = 0x87, - [0x68] = 0x88, [0x69] = 0x89, [0x6A] = 0x91, [0x6B] = 0x92, - [0x6C] = 0x93, [0x6D] = 0x94, [0x6E] = 0x95, [0x6F] = 0x96, - [0x70] = 0x97, [0x71] = 0x98, [0x72] = 0x99, [0x73] = 0xA2, - [0x74] = 0xA3, [0x75] = 0xA4, [0x76] = 0xA5, [0x77] = 0xA6, - [0x78] = 0xA7, [0x79] = 0xA8, [0x7A] = 0xA9, [0x7B] = 0xCE, - [0x7C] = 0x4F, [0x7D] = 0xE1, [0x7E] = 0xEC, [0x7F] = 0x07, - [0x80] = 0x20, [0x81] = 0x21, [0x82] = 0x22, [0x83] = 0x23, - [0x84] = 0x24, [0x85] = 0x15, [0x86] = 0x06, [0x87] = 0x17, - [0x88] = 0x28, [0x89] = 0x29, [0x8A] = 0x2A, [0x8B] = 0x2B, - [0x8C] = 0x2C, [0x8D] = 0x09, [0x8E] = 0x0A, [0x8F] = 0x1B, - [0x90] = 0x30, [0x91] = 0x31, [0x92] = 0x1A, [0x93] = 0x33, - [0x94] = 0x34, [0x95] = 0x35, [0x96] = 0x36, [0x97] = 0x08, - [0x98] = 0x38, [0x99] = 0x39, [0x9A] = 0x3A, [0x9B] = 0x3B, - [0x9C] = 0x04, [0x9D] = 0x14, [0x9E] = 0x3E, [0x9F] = 0xFF, - [0xA0] = 0x41, [0xA1] = 0x79, [0xA2] = 0x4A, [0xA3] = 0xC0, - [0xA4] = 0xD0, [0xA5] = 0x42, [0xA6] = 0x6A, [0xA7] = 0x43, - [0xA8] = 0x44, [0xA9] = 0x45, [0xAA] = 0x46, [0xAB] = 0x47, - [0xAC] = 0x5F, [0xAD] = 0xCA, [0xAE] = 0x48, [0xAF] = 0x49, - [0xB0] = 0xDF, [0xB1] = 0xEA, [0xB2] = 0xEB, [0xB3] = 0xED, - [0xB4] = 0xEE, [0xB5] = 0xEF, [0xB6] = 0xFB, [0xB7] = 0xFC, - [0xB8] = 0xFD, [0xB9] = 0xFE, [0xBA] = 0x51, [0xBB] = 0x52, - [0xBC] = 0x55, [0xBD] = 0x56, [0xBE] = 0x57, [0xBF] = 0x58, - [0xC0] = 0x59, [0xC1] = 0x62, [0xC2] = 0x63, [0xC3] = 0x64, - [0xC4] = 0x65, [0xC5] = 0x66, [0xC6] = 0x67, [0xC7] = 0x68, - [0xC8] = 0x69, [0xC9] = 0x70, [0xCA] = 0x71, [0xCB] = 0x72, - [0xCC] = 0x73, [0xCD] = 0x74, [0xCE] = 0x75, [0xCF] = 0x76, - [0xD0] = 0x77, [0xD1] = 0x78, [0xD2] = 0x80, [0xD3] = 0x8A, - [0xD4] = 0x8B, [0xD5] = 0x8C, [0xD6] = 0x8D, [0xD7] = 0xE0, - [0xD8] = 0x8E, [0xD9] = 0x8F, [0xDA] = 0x90, [0xDB] = 0x9A, - [0xDC] = 0x9B, [0xDD] = 0x9C, [0xDE] = 0x9D, [0xDF] = 0x9E, - [0xE0] = 0x9F, [0xE1] = 0xA0, [0xE2] = 0xAA, [0xE3] = 0xAB, - [0xE4] = 0xAC, [0xE5] = 0xAD, [0xE6] = 0xAE, [0xE7] = 0xAF, - [0xE8] = 0xB0, [0xE9] = 0xB1, [0xEA] = 0xB2, [0xEB] = 0xB3, - [0xEC] = 0xB4, [0xED] = 0xB5, [0xEE] = 0xB8, [0xEF] = 0xB9, - [0xF0] = 0xBA, [0xF1] = 0xBB, [0xF2] = 0xBC, [0xF3] = 0xBD, - [0xF4] = 0xBE, [0xF5] = 0xBF, [0xF6] = 0xCB, [0xF7] = 0xA1, - [0xF8] = 0xCD, [0xF9] = 0xCF, [0xFA] = 0xDA, [0xFB] = 0xDB, - [0xFC] = 0xDC, [0xFD] = 0xDD, [0xFE] = 0xDE, [0xFF] = 0xFA, + [0x00] = 0x00, [0x01] = 0x01, [0x02] = 0x02, [0x03] = 0x03, + [0x04] = 0x37, [0x05] = 0x2D, [0x06] = 0x2E, [0x07] = 0x2F, + [0x08] = 0x16, [0x09] = 0x05, [0x0A] = 0x25, [0x0B] = 0x0B, + [0x0C] = 0x0C, [0x0D] = 0x0D, [0x0E] = 0x0E, [0x0F] = 0x0F, + [0x10] = 0x10, [0x11] = 0x11, [0x12] = 0x12, [0x13] = 0x13, + [0x14] = 0x3C, [0x15] = 0x3D, [0x16] = 0x32, [0x17] = 0x26, + [0x18] = 0x18, [0x19] = 0x19, [0x1A] = 0x3F, [0x1B] = 0x27, + [0x1C] = 0x1C, [0x1D] = 0x1D, [0x1E] = 0x1E, [0x1F] = 0x1F, + [0x20] = 0x40, [0x21] = 0x5A, [0x22] = 0x7F, [0x23] = 0x7B, + [0x24] = 0x5B, [0x25] = 0x6C, [0x26] = 0x50, [0x27] = 0x7D, + [0x28] = 0x4D, [0x29] = 0x5D, [0x2A] = 0x5C, [0x2B] = 0x4E, + [0x2C] = 0x6B, [0x2D] = 0x60, [0x2E] = 0x4B, [0x2F] = 0x61, + [0x30] = 0xF0, [0x31] = 0xF1, [0x32] = 0xF2, [0x33] = 0xF3, + [0x34] = 0xF4, [0x35] = 0xF5, [0x36] = 0xF6, [0x37] = 0xF7, + [0x38] = 0xF8, [0x39] = 0xF9, [0x3A] = 0x7A, [0x3B] = 0x5E, + [0x3C] = 0x4C, [0x3D] = 0x7E, [0x3E] = 0x6E, [0x3F] = 0x6F, + [0x40] = 0x7C, [0x41] = 0xC1, [0x42] = 0xC2, [0x43] = 0xC3, + [0x44] = 0xC4, [0x45] = 0xC5, [0x46] = 0xC6, [0x47] = 0xC7, + [0x48] = 0xC8, [0x49] = 0xC9, [0x4A] = 0xD1, [0x4B] = 0xD2, + [0x4C] = 0xD3, [0x4D] = 0xD4, [0x4E] = 0xD5, [0x4F] = 0xD6, + [0x50] = 0xD7, [0x51] = 0xD8, [0x52] = 0xD9, [0x53] = 0xE2, + [0x54] = 0xE3, [0x55] = 0xE4, [0x56] = 0xE5, [0x57] = 0xE6, + [0x58] = 0xE7, [0x59] = 0xE8, [0x5A] = 0xE9, [0x5B] = 0x53, + [0x5C] = 0x54, [0x5D] = 0xB6, [0x5E] = 0xB7, [0x5F] = 0x6D, + [0x60] = 0xCC, [0x61] = 0x81, [0x62] = 0x82, [0x63] = 0x83, + [0x64] = 0x84, [0x65] = 0x85, [0x66] = 0x86, [0x67] = 0x87, + [0x68] = 0x88, [0x69] = 0x89, [0x6A] = 0x91, [0x6B] = 0x92, + [0x6C] = 0x93, [0x6D] = 0x94, [0x6E] = 0x95, [0x6F] = 0x96, + [0x70] = 0x97, [0x71] = 0x98, [0x72] = 0x99, [0x73] = 0xA2, + [0x74] = 0xA3, [0x75] = 0xA4, [0x76] = 0xA5, [0x77] = 0xA6, + [0x78] = 0xA7, [0x79] = 0xA8, [0x7A] = 0xA9, [0x7B] = 0xCE, + [0x7C] = 0x4F, [0x7D] = 0xE1, [0x7E] = 0xEC, [0x7F] = 0x07, + [0x80] = 0x20, [0x81] = 0x21, [0x82] = 0x22, [0x83] = 0x23, + [0x84] = 0x24, [0x85] = 0x15, [0x86] = 0x06, [0x87] = 0x17, + [0x88] = 0x28, [0x89] = 0x29, [0x8A] = 0x2A, [0x8B] = 0x2B, + [0x8C] = 0x2C, [0x8D] = 0x09, [0x8E] = 0x0A, [0x8F] = 0x1B, + [0x90] = 0x30, [0x91] = 0x31, [0x92] = 0x1A, [0x93] = 0x33, + [0x94] = 0x34, [0x95] = 0x35, [0x96] = 0x36, [0x97] = 0x08, + [0x98] = 0x38, [0x99] = 0x39, [0x9A] = 0x3A, [0x9B] = 0x3B, + [0x9C] = 0x04, [0x9D] = 0x14, [0x9E] = 0x3E, [0x9F] = 0xFF, + [0xA0] = 0x41, [0xA1] = 0x79, [0xA2] = 0x4A, [0xA3] = 0xC0, + [0xA4] = 0xD0, [0xA5] = 0x42, [0xA6] = 0x6A, [0xA7] = 0x43, + [0xA8] = 0x44, [0xA9] = 0x45, [0xAA] = 0x46, [0xAB] = 0x47, + [0xAC] = 0x5F, [0xAD] = 0xCA, [0xAE] = 0x48, [0xAF] = 0x49, + [0xB0] = 0xDF, [0xB1] = 0xEA, [0xB2] = 0xEB, [0xB3] = 0xED, + [0xB4] = 0xEE, [0xB5] = 0xEF, [0xB6] = 0xFB, [0xB7] = 0xFC, + [0xB8] = 0xFD, [0xB9] = 0xFE, [0xBA] = 0x51, [0xBB] = 0x52, + [0xBC] = 0x55, [0xBD] = 0x56, [0xBE] = 0x57, [0xBF] = 0x58, + [0xC0] = 0x59, [0xC1] = 0x62, [0xC2] = 0x63, [0xC3] = 0x64, + [0xC4] = 0x65, [0xC5] = 0x66, [0xC6] = 0x67, [0xC7] = 0x68, + [0xC8] = 0x69, [0xC9] = 0x70, [0xCA] = 0x71, [0xCB] = 0x72, + [0xCC] = 0x73, [0xCD] = 0x74, [0xCE] = 0x75, [0xCF] = 0x76, + [0xD0] = 0x77, [0xD1] = 0x78, [0xD2] = 0x80, [0xD3] = 0x8A, + [0xD4] = 0x8B, [0xD5] = 0x8C, [0xD6] = 0x8D, [0xD7] = 0xE0, + [0xD8] = 0x8E, [0xD9] = 0x8F, [0xDA] = 0x90, [0xDB] = 0x9A, + [0xDC] = 0x9B, [0xDD] = 0x9C, [0xDE] = 0x9D, [0xDF] = 0x9E, + [0xE0] = 0x9F, [0xE1] = 0xA0, [0xE2] = 0xAA, [0xE3] = 0xAB, + [0xE4] = 0xAC, [0xE5] = 0xAD, [0xE6] = 0xAE, [0xE7] = 0xAF, + [0xE8] = 0xB0, [0xE9] = 0xB1, [0xEA] = 0xB2, [0xEB] = 0xB3, + [0xEC] = 0xB4, [0xED] = 0xB5, [0xEE] = 0xB8, [0xEF] = 0xB9, + [0xF0] = 0xBA, [0xF1] = 0xBB, [0xF2] = 0xBC, [0xF3] = 0xBD, + [0xF4] = 0xBE, [0xF5] = 0xBF, [0xF6] = 0xCB, [0xF7] = 0xA1, + [0xF8] = 0xCD, [0xF9] = 0xCF, [0xFA] = 0xDA, [0xFB] = 0xDB, + [0xFC] = 0xDC, [0xFD] = 0xDD, [0xFE] = 0xDE, [0xFF] = 0xFA, }; static const char __from_ibm420_to_ibm1008[256] = { - [0x00] = 0x00, [0x01] = 0x01, [0x02] = 0x02, [0x03] = 0x03, - [0x04] = 0x9C, [0x05] = 0x09, [0x06] = 0x86, [0x07] = 0x7F, - [0x08] = 0x97, [0x09] = 0x8D, [0x0A] = 0x8E, [0x0B] = 0x0B, - [0x0C] = 0x0C, [0x0D] = 0x0D, [0x0E] = 0x0E, [0x0F] = 0x0F, - [0x10] = 0x10, [0x11] = 0x11, [0x12] = 0x12, [0x13] = 0x13, - [0x14] = 0x9D, [0x15] = 0x85, [0x16] = 0x08, [0x17] = 0x87, - [0x18] = 0x18, [0x19] = 0x19, [0x1A] = 0x92, [0x1B] = 0x8F, - [0x1C] = 0x1C, [0x1D] = 0x1D, [0x1E] = 0x1E, [0x1F] = 0x1F, - [0x20] = 0x80, [0x21] = 0x81, [0x22] = 0x82, [0x23] = 0x83, - [0x24] = 0x84, [0x25] = 0x0A, [0x26] = 0x17, [0x27] = 0x1B, - [0x28] = 0x88, [0x29] = 0x89, [0x2A] = 0x8A, [0x2B] = 0x8B, - [0x2C] = 0x8C, [0x2D] = 0x05, [0x2E] = 0x06, [0x2F] = 0x07, - [0x30] = 0x90, [0x31] = 0x91, [0x32] = 0x16, [0x33] = 0x93, - [0x34] = 0x94, [0x35] = 0x95, [0x36] = 0x96, [0x37] = 0x04, - [0x38] = 0x98, [0x39] = 0x99, [0x3A] = 0x9A, [0x3B] = 0x9B, - [0x3C] = 0x14, [0x3D] = 0x15, [0x3E] = 0x9E, [0x3F] = 0x1A, - [0x40] = 0x20, [0x41] = 0xA0, [0x42] = 0xA5, [0x43] = 0xA7, - [0x44] = 0xA8, [0x45] = 0xA9, [0x46] = 0xAA, [0x47] = 0xAB, - [0x48] = 0xAE, [0x49] = 0xAF, [0x4A] = 0xA2, [0x4B] = 0x2E, - [0x4C] = 0x3C, [0x4D] = 0x28, [0x4E] = 0x2B, [0x4F] = 0x7C, - [0x50] = 0x26, [0x51] = 0xBA, [0x52] = 0xBB, [0x53] = 0x5B, - [0x54] = 0x5C, [0x55] = 0xBC, [0x56] = 0xBD, [0x57] = 0xBE, - [0x58] = 0xBF, [0x59] = 0xC0, [0x5A] = 0x21, [0x5B] = 0x24, - [0x5C] = 0x2A, [0x5D] = 0x29, [0x5E] = 0x3B, [0x5F] = 0xAC, - [0x60] = 0x2D, [0x61] = 0x2F, [0x62] = 0xC1, [0x63] = 0xC2, - [0x64] = 0xC3, [0x65] = 0xC4, [0x66] = 0xC5, [0x67] = 0xC6, - [0x68] = 0xC7, [0x69] = 0xC8, [0x6A] = 0xA6, [0x6B] = 0x2C, - [0x6C] = 0x25, [0x6D] = 0x5F, [0x6E] = 0x3E, [0x6F] = 0x3F, - [0x70] = 0xC9, [0x71] = 0xCA, [0x72] = 0xCB, [0x73] = 0xCC, - [0x74] = 0xCD, [0x75] = 0xCE, [0x76] = 0xCF, [0x77] = 0xD0, - [0x78] = 0xD1, [0x79] = 0xA1, [0x7A] = 0x3A, [0x7B] = 0x23, - [0x7C] = 0x40, [0x7D] = 0x27, [0x7E] = 0x3D, [0x7F] = 0x22, - [0x80] = 0xD2, [0x81] = 0x61, [0x82] = 0x62, [0x83] = 0x63, - [0x84] = 0x64, [0x85] = 0x65, [0x86] = 0x66, [0x87] = 0x67, - [0x88] = 0x68, [0x89] = 0x69, [0x8A] = 0xD3, [0x8B] = 0xD4, - [0x8C] = 0xD5, [0x8D] = 0xD6, [0x8E] = 0xD8, [0x8F] = 0xD9, - [0x90] = 0xDA, [0x91] = 0x6A, [0x92] = 0x6B, [0x93] = 0x6C, - [0x94] = 0x6D, [0x95] = 0x6E, [0x96] = 0x6F, [0x97] = 0x70, - [0x98] = 0x71, [0x99] = 0x72, [0x9A] = 0xDB, [0x9B] = 0xDC, - [0x9C] = 0xDD, [0x9D] = 0xDE, [0x9E] = 0xDF, [0x9F] = 0xE0, - [0xA0] = 0xE1, [0xA1] = 0xF7, [0xA2] = 0x73, [0xA3] = 0x74, - [0xA4] = 0x75, [0xA5] = 0x76, [0xA6] = 0x77, [0xA7] = 0x78, - [0xA8] = 0x79, [0xA9] = 0x7A, [0xAA] = 0xE2, [0xAB] = 0xE3, - [0xAC] = 0xE4, [0xAD] = 0xE5, [0xAE] = 0xE6, [0xAF] = 0xE7, - [0xB0] = 0xE8, [0xB1] = 0xE9, [0xB2] = 0xEA, [0xB3] = 0xEB, - [0xB4] = 0xEC, [0xB5] = 0xED, [0xB6] = 0x5D, [0xB7] = 0x5E, - [0xB8] = 0xEE, [0xB9] = 0xEF, [0xBA] = 0xF0, [0xBB] = 0xF1, - [0xBC] = 0xF2, [0xBD] = 0xF3, [0xBE] = 0xF4, [0xBF] = 0xF5, - [0xC0] = 0xA3, [0xC1] = 0x41, [0xC2] = 0x42, [0xC3] = 0x43, - [0xC4] = 0x44, [0xC5] = 0x45, [0xC6] = 0x46, [0xC7] = 0x47, - [0xC8] = 0x48, [0xC9] = 0x49, [0xCA] = 0xAD, [0xCB] = 0xF6, - [0xCC] = 0x60, [0xCD] = 0xF8, [0xCE] = 0x7B, [0xCF] = 0xF9, - [0xD0] = 0xA4, [0xD1] = 0x4A, [0xD2] = 0x4B, [0xD3] = 0x4C, - [0xD4] = 0x4D, [0xD5] = 0x4E, [0xD6] = 0x4F, [0xD7] = 0x50, - [0xD8] = 0x51, [0xD9] = 0x52, [0xDA] = 0xFA, [0xDB] = 0xFB, - [0xDC] = 0xFC, [0xDD] = 0xFD, [0xDE] = 0xFE, [0xDF] = 0xB0, - [0xE0] = 0xD7, [0xE1] = 0x7D, [0xE2] = 0x53, [0xE3] = 0x54, - [0xE4] = 0x55, [0xE5] = 0x56, [0xE6] = 0x57, [0xE7] = 0x58, - [0xE8] = 0x59, [0xE9] = 0x5A, [0xEA] = 0xB1, [0xEB] = 0xB2, - [0xEC] = 0x7E, [0xED] = 0xB3, [0xEE] = 0xB4, [0xEF] = 0xB5, - [0xF0] = 0x30, [0xF1] = 0x31, [0xF2] = 0x32, [0xF3] = 0x33, - [0xF4] = 0x34, [0xF5] = 0x35, [0xF6] = 0x36, [0xF7] = 0x37, - [0xF8] = 0x38, [0xF9] = 0x39, [0xFA] = 0xFF, [0xFB] = 0xB6, - [0xFC] = 0xB7, [0xFD] = 0xB8, [0xFE] = 0xB9, [0xFF] = 0x9F, + [0x00] = 0x00, [0x01] = 0x01, [0x02] = 0x02, [0x03] = 0x03, + [0x04] = 0x9C, [0x05] = 0x09, [0x06] = 0x86, [0x07] = 0x7F, + [0x08] = 0x97, [0x09] = 0x8D, [0x0A] = 0x8E, [0x0B] = 0x0B, + [0x0C] = 0x0C, [0x0D] = 0x0D, [0x0E] = 0x0E, [0x0F] = 0x0F, + [0x10] = 0x10, [0x11] = 0x11, [0x12] = 0x12, [0x13] = 0x13, + [0x14] = 0x9D, [0x15] = 0x85, [0x16] = 0x08, [0x17] = 0x87, + [0x18] = 0x18, [0x19] = 0x19, [0x1A] = 0x92, [0x1B] = 0x8F, + [0x1C] = 0x1C, [0x1D] = 0x1D, [0x1E] = 0x1E, [0x1F] = 0x1F, + [0x20] = 0x80, [0x21] = 0x81, [0x22] = 0x82, [0x23] = 0x83, + [0x24] = 0x84, [0x25] = 0x0A, [0x26] = 0x17, [0x27] = 0x1B, + [0x28] = 0x88, [0x29] = 0x89, [0x2A] = 0x8A, [0x2B] = 0x8B, + [0x2C] = 0x8C, [0x2D] = 0x05, [0x2E] = 0x06, [0x2F] = 0x07, + [0x30] = 0x90, [0x31] = 0x91, [0x32] = 0x16, [0x33] = 0x93, + [0x34] = 0x94, [0x35] = 0x95, [0x36] = 0x96, [0x37] = 0x04, + [0x38] = 0x98, [0x39] = 0x99, [0x3A] = 0x9A, [0x3B] = 0x9B, + [0x3C] = 0x14, [0x3D] = 0x15, [0x3E] = 0x9E, [0x3F] = 0x1A, + [0x40] = 0x20, [0x41] = 0xA0, [0x42] = 0xA5, [0x43] = 0xA7, + [0x44] = 0xA8, [0x45] = 0xA9, [0x46] = 0xAA, [0x47] = 0xAB, + [0x48] = 0xAE, [0x49] = 0xAF, [0x4A] = 0xA2, [0x4B] = 0x2E, + [0x4C] = 0x3C, [0x4D] = 0x28, [0x4E] = 0x2B, [0x4F] = 0x7C, + [0x50] = 0x26, [0x51] = 0xBA, [0x52] = 0xBB, [0x53] = 0x5B, + [0x54] = 0x5C, [0x55] = 0xBC, [0x56] = 0xBD, [0x57] = 0xBE, + [0x58] = 0xBF, [0x59] = 0xC0, [0x5A] = 0x21, [0x5B] = 0x24, + [0x5C] = 0x2A, [0x5D] = 0x29, [0x5E] = 0x3B, [0x5F] = 0xAC, + [0x60] = 0x2D, [0x61] = 0x2F, [0x62] = 0xC1, [0x63] = 0xC2, + [0x64] = 0xC3, [0x65] = 0xC4, [0x66] = 0xC5, [0x67] = 0xC6, + [0x68] = 0xC7, [0x69] = 0xC8, [0x6A] = 0xA6, [0x6B] = 0x2C, + [0x6C] = 0x25, [0x6D] = 0x5F, [0x6E] = 0x3E, [0x6F] = 0x3F, + [0x70] = 0xC9, [0x71] = 0xCA, [0x72] = 0xCB, [0x73] = 0xCC, + [0x74] = 0xCD, [0x75] = 0xCE, [0x76] = 0xCF, [0x77] = 0xD0, + [0x78] = 0xD1, [0x79] = 0xA1, [0x7A] = 0x3A, [0x7B] = 0x23, + [0x7C] = 0x40, [0x7D] = 0x27, [0x7E] = 0x3D, [0x7F] = 0x22, + [0x80] = 0xD2, [0x81] = 0x61, [0x82] = 0x62, [0x83] = 0x63, + [0x84] = 0x64, [0x85] = 0x65, [0x86] = 0x66, [0x87] = 0x67, + [0x88] = 0x68, [0x89] = 0x69, [0x8A] = 0xD3, [0x8B] = 0xD4, + [0x8C] = 0xD5, [0x8D] = 0xD6, [0x8E] = 0xD8, [0x8F] = 0xD9, + [0x90] = 0xDA, [0x91] = 0x6A, [0x92] = 0x6B, [0x93] = 0x6C, + [0x94] = 0x6D, [0x95] = 0x6E, [0x96] = 0x6F, [0x97] = 0x70, + [0x98] = 0x71, [0x99] = 0x72, [0x9A] = 0xDB, [0x9B] = 0xDC, + [0x9C] = 0xDD, [0x9D] = 0xDE, [0x9E] = 0xDF, [0x9F] = 0xE0, + [0xA0] = 0xE1, [0xA1] = 0xF7, [0xA2] = 0x73, [0xA3] = 0x74, + [0xA4] = 0x75, [0xA5] = 0x76, [0xA6] = 0x77, [0xA7] = 0x78, + [0xA8] = 0x79, [0xA9] = 0x7A, [0xAA] = 0xE2, [0xAB] = 0xE3, + [0xAC] = 0xE4, [0xAD] = 0xE5, [0xAE] = 0xE6, [0xAF] = 0xE7, + [0xB0] = 0xE8, [0xB1] = 0xE9, [0xB2] = 0xEA, [0xB3] = 0xEB, + [0xB4] = 0xEC, [0xB5] = 0xED, [0xB6] = 0x5D, [0xB7] = 0x5E, + [0xB8] = 0xEE, [0xB9] = 0xEF, [0xBA] = 0xF0, [0xBB] = 0xF1, + [0xBC] = 0xF2, [0xBD] = 0xF3, [0xBE] = 0xF4, [0xBF] = 0xF5, + [0xC0] = 0xA3, [0xC1] = 0x41, [0xC2] = 0x42, [0xC3] = 0x43, + [0xC4] = 0x44, [0xC5] = 0x45, [0xC6] = 0x46, [0xC7] = 0x47, + [0xC8] = 0x48, [0xC9] = 0x49, [0xCA] = 0xAD, [0xCB] = 0xF6, + [0xCC] = 0x60, [0xCD] = 0xF8, [0xCE] = 0x7B, [0xCF] = 0xF9, + [0xD0] = 0xA4, [0xD1] = 0x4A, [0xD2] = 0x4B, [0xD3] = 0x4C, + [0xD4] = 0x4D, [0xD5] = 0x4E, [0xD6] = 0x4F, [0xD7] = 0x50, + [0xD8] = 0x51, [0xD9] = 0x52, [0xDA] = 0xFA, [0xDB] = 0xFB, + [0xDC] = 0xFC, [0xDD] = 0xFD, [0xDE] = 0xFE, [0xDF] = 0xB0, + [0xE0] = 0xD7, [0xE1] = 0x7D, [0xE2] = 0x53, [0xE3] = 0x54, + [0xE4] = 0x55, [0xE5] = 0x56, [0xE6] = 0x57, [0xE7] = 0x58, + [0xE8] = 0x59, [0xE9] = 0x5A, [0xEA] = 0xB1, [0xEB] = 0xB2, + [0xEC] = 0x7E, [0xED] = 0xB3, [0xEE] = 0xB4, [0xEF] = 0xB5, + [0xF0] = 0x30, [0xF1] = 0x31, [0xF2] = 0x32, [0xF3] = 0x33, + [0xF4] = 0x34, [0xF5] = 0x35, [0xF6] = 0x36, [0xF7] = 0x37, + [0xF8] = 0x38, [0xF9] = 0x39, [0xFA] = 0xFF, [0xFB] = 0xB6, + [0xFC] = 0xB7, [0xFD] = 0xB8, [0xFE] = 0xB9, [0xFF] = 0x9F, }; #define CHARSET_NAME "IBM1008//" diff --git a/inet/tst-getni1.c b/inet/tst-getni1.c index 0e8a792..3960f71 100644 --- a/inet/tst-getni1.c +++ b/inet/tst-getni1.c @@ -19,7 +19,7 @@ do_test (void) puts ("failed without NI_NAMEREQD"); retval = 1; } - + r = getnameinfo((struct sockaddr *) &s, sizeof (s), NULL, 0, NULL, 0, NI_NUMERICHOST | NI_NUMERICSERV | NI_NAMEREQD); printf("r = %d\n", r); diff --git a/inet/tst-getni2.c b/inet/tst-getni2.c index b949d88..66e7806 100644 --- a/inet/tst-getni2.c +++ b/inet/tst-getni2.c @@ -23,7 +23,7 @@ do_test (void) puts ("failed without NI_NAMEREQD"); retval = 1; } - + buf[0] = '\0'; r = getnameinfo((struct sockaddr *) &s, sizeof (s), buf, sizeof (buf), NULL, 0, NI_NUMERICSERV | NI_NAMEREQD); diff --git a/libio/ioungetc.c b/libio/ioungetc.c index f2e1b27..1865694 100644 --- a/libio/ioungetc.c +++ b/libio/ioungetc.c @@ -35,7 +35,7 @@ _IO_ungetc (c, fp) CHECK_FILE (fp, EOF); if (c == EOF) return EOF; - _IO_acquire_lock (fp); + _IO_acquire_lock (fp); result = _IO_sputbackc (fp, (unsigned char) c); _IO_release_lock (fp); return result; diff --git a/libio/wfiledoalloc.c b/libio/wfiledoalloc.c index 14501f2..4a900a8 100644 --- a/libio/wfiledoalloc.c +++ b/libio/wfiledoalloc.c @@ -27,7 +27,7 @@ /* Copyright (C) 1990 The Regents of the University of California. All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,7 +40,7 @@ 4. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE diff --git a/manual/libm-err-tab.pl b/manual/libm-err-tab.pl index 1564669..7c213fd 100755 --- a/manual/libm-err-tab.pl +++ b/manual/libm-err-tab.pl @@ -235,6 +235,6 @@ sub by_platforms { $pa = $pplatforms{$a} ? $pplatforms{$a} : $a; $pb = $pplatforms{$b} ? $pplatforms{$b} : $b; - + return $pa cmp $pb; } diff --git a/math/w_dremf.c b/math/w_dremf.c index 4ec4baf..0e25ef8 100644 --- a/math/w_dremf.c +++ b/math/w_dremf.c @@ -1,6 +1,6 @@ /* * dremf() wrapper for remainderf(). - * + * * Written by J.T. Conklin, <jtc@wimsey.com> * Placed into the Public Domain, 1994. */ diff --git a/misc/ftruncate.c b/misc/ftruncate.c index 80830f8..7b38b17 100644 --- a/misc/ftruncate.c +++ b/misc/ftruncate.c @@ -30,5 +30,5 @@ __ftruncate (fd, length) } weak_alias (__ftruncate, ftruncate) - + stub_warning (ftruncate) diff --git a/posix/bug-glob2.c b/posix/bug-glob2.c index a8ffcb0..abae19b 100644 --- a/posix/bug-glob2.c +++ b/posix/bug-glob2.c @@ -276,7 +276,7 @@ do_test (void) != GLOB_ABORTED) { puts ("glob did not fail with GLOB_ABORTED"); - exit (EXIT_FAILURE); + exit (EXIT_FAILURE); } globfree (&gl); @@ -288,7 +288,7 @@ do_test (void) if (glob ("dir2/*", GLOB_DOOFFS, NULL, &gl) != GLOB_NOMATCH) { puts ("glob did not fail with GLOB_NOMATCH"); - exit (EXIT_FAILURE); + exit (EXIT_FAILURE); } globfree (&gl); diff --git a/posix/tst-pcre.c b/posix/tst-pcre.c index 5a2dcd6..afae926 100644 --- a/posix/tst-pcre.c +++ b/posix/tst-pcre.c @@ -132,7 +132,7 @@ main (int argc, char **argv) { regex_t re; int n; - + if (!pattern_valid) { printf ("%zd: No previous valid pattern %s\n", linenum, line); diff --git a/posix/wait4.c b/posix/wait4.c index fd23da5..e55f71d 100644 --- a/posix/wait4.c +++ b/posix/wait4.c @@ -20,7 +20,7 @@ #include <errno.h> pid_t -__wait4 (__pid_t pid, __WAIT_STATUS stat_loc, int options, +__wait4 (__pid_t pid, __WAIT_STATUS stat_loc, int options, struct rusage *usage) { __set_errno (ENOSYS); diff --git a/resolv/README b/resolv/README index 416205d..dbb1510 100644 --- a/resolv/README +++ b/resolv/README @@ -62,7 +62,7 @@ the `gethostby*' family of functions, which means that for example traditional resolver interfaces however, continue to use a single resolver state and are therefore still thread-unsafe. The resolver state is the same resolver state that is used for the initial ("main") -thread. +thread. This has the following consequences for existing binaries and source code: diff --git a/resolv/res_debug.h b/resolv/res_debug.h index 4a0aa99..2d8ad15 100644 --- a/resolv/res_debug.h +++ b/resolv/res_debug.h @@ -31,4 +31,4 @@ } else {} #endif -#endif /* _RES_DEBUG_H_ */ +#endif /* _RES_DEBUG_H_ */ diff --git a/resolv/tst-inet_ntop.c b/resolv/tst-inet_ntop.c index a042c74..f968ec4 100644 --- a/resolv/tst-inet_ntop.c +++ b/resolv/tst-inet_ntop.c @@ -106,6 +106,6 @@ main (void) result++; } - + return result; } diff --git a/setjmp/bug269-setjmp.c b/setjmp/bug269-setjmp.c index b982f6b..7521cee 100644 --- a/setjmp/bug269-setjmp.c +++ b/setjmp/bug269-setjmp.c @@ -29,7 +29,7 @@ int n_x = 6; static int g_counter = 0; int -f (void) +f (void) { static int counter = 0; static int way_point1 = 3; diff --git a/soft-fp/extended.h b/soft-fp/extended.h index a4bd7e8..7492755 100644 --- a/soft-fp/extended.h +++ b/soft-fp/extended.h @@ -203,7 +203,7 @@ union _FP_UNION_E * anyway, we optimize it by doing most of the calculations * in two UWtype registers instead of four. */ - + #define _FP_SQRT_MEAT_E(R, S, T, X, q) \ do { \ q = (_FP_W_TYPE)1 << (_FP_W_TYPE_SIZE - 1); \ @@ -416,7 +416,7 @@ union _FP_UNION_E R##_f0 |= _FP_WORK_STICKY; \ } \ } while (0) - + #define FP_CMP_E(r,X,Y,un) _FP_CMP(E,2,r,X,Y,un) #define FP_CMP_EQ_E(r,X,Y) _FP_CMP_EQ(E,2,r,X,Y) #define FP_CMP_UNORD_E(r,X,Y) _FP_CMP_UNORD(E,2,r,X,Y) diff --git a/soft-fp/op-1.h b/soft-fp/op-1.h index 30e6063..b9035ee 100644 --- a/soft-fp/op-1.h +++ b/soft-fp/op-1.h @@ -255,14 +255,14 @@ do { \ udiv_qrnnd(_q, _r, _nh, _nl, Y##_f); \ R##_f = _q | (_r != 0); \ } while (0) - - + + /* * Square root algorithms: * We have just one right now, maybe Newton approximation * should be added for those machines where division is fast. */ - + #define _FP_SQRT_MEAT_1(R, S, T, X, q) \ do { \ while (q != _FP_WORK_ROUND) \ @@ -286,7 +286,7 @@ do { \ } while (0) /* - * Assembly/disassembly for converting to/from integral types. + * Assembly/disassembly for converting to/from integral types. * No shifting or overflow handled here. */ diff --git a/soft-fp/op-2.h b/soft-fp/op-2.h index 1b63c8c..f25af19 100644 --- a/soft-fp/op-2.h +++ b/soft-fp/op-2.h @@ -145,7 +145,7 @@ #define _FP_MAXFRAC_2 (~(_FP_WS_TYPE)0), (~(_FP_WS_TYPE)0) /* - * Internals + * Internals */ #define __FP_FRAC_SET_2(X,I1,I0) (X##_f0 = I0, X##_f1 = I1) @@ -348,7 +348,7 @@ point multiplication. This is useful if floating point multiplication has much bigger throughput than integer multiply. It is supposed to work for _FP_W_TYPE_SIZE 64 and wfracbits - between 106 and 120 only. + between 106 and 120 only. Caller guarantees that X and Y has (1LLL << (wfracbits - 1)) set. SETFETZ is a macro which will disable all FPU exceptions and set rounding towards zero, RESETFE should optionally reset it back. */ @@ -544,7 +544,7 @@ * We have just one right now, maybe Newton approximation * should be added for those machines where division is fast. */ - + #define _FP_SQRT_MEAT_2(R, S, T, X, q) \ do { \ while (q) \ @@ -586,7 +586,7 @@ /* - * Assembly/disassembly for converting to/from integral types. + * Assembly/disassembly for converting to/from integral types. * No shifting or overflow handled here. */ diff --git a/soft-fp/op-4.h b/soft-fp/op-4.h index a9d421a..9b5caa7 100644 --- a/soft-fp/op-4.h +++ b/soft-fp/op-4.h @@ -81,7 +81,7 @@ } while (0) -/* Right shift with sticky-lsb. +/* Right shift with sticky-lsb. * What this actually means is that we do a standard right-shift, * but that if any of the bits that fall off the right hand side * were one then we always set the LSbit. @@ -435,7 +435,7 @@ * We have just one right now, maybe Newton approximation * should be added for those machines where division is fast. */ - + #define _FP_SQRT_MEAT_4(R, S, T, X, q) \ do { \ while (q) \ @@ -516,7 +516,7 @@ /* - * Internals + * Internals */ #define __FP_FRAC_SET_4(X,I3,I2,I1,I0) \ @@ -618,9 +618,9 @@ /* Convert FP values between word sizes. This appears to be more * complicated than I'd have expected it to be, so these might be * wrong... These macros are in any case somewhat bogus because they - * use information about what various FRAC_n variables look like + * use information about what various FRAC_n variables look like * internally [eg, that 2 word vars are X_f0 and x_f1]. But so do - * the ones in op-2.h and op-1.h. + * the ones in op-2.h and op-1.h. */ #define _FP_FRAC_COPY_1_4(D, S) (D##_f = S##_f[0]) @@ -630,7 +630,7 @@ do { \ D##_f1 = S##_f[1]; \ } while (0) -/* Assembly/disassembly for converting to/from integral types. +/* Assembly/disassembly for converting to/from integral types. * No shifting or overflow handled here. */ /* Put the FP value X into r, which is an integer of size rsize. */ diff --git a/soft-fp/op-8.h b/soft-fp/op-8.h index 9bb9232..8890d02 100644 --- a/soft-fp/op-8.h +++ b/soft-fp/op-8.h @@ -77,7 +77,7 @@ } while (0) -/* Right shift with sticky-lsb. +/* Right shift with sticky-lsb. * What this actually means is that we do a standard right-shift, * but that if any of the bits that fall off the right hand side * were one then we always set the LSbit. diff --git a/soft-fp/testit.c b/soft-fp/testit.c index f1e9b54..1aaf8b4 100644 --- a/soft-fp/testit.c +++ b/soft-fp/testit.c @@ -244,7 +244,7 @@ float build_float(const char *s, const char *e, const char *f) return u.flt; } - + double build_double(const char *s, const char *e, const char *f) { union _FP_UNION_D u; @@ -264,10 +264,10 @@ double build_double(const char *s, const char *e, const char *f) #else u.bits.frac = strtoul(f, 0, 16); #endif - + return u.flt; } - + /*======================================================================*/ fpu_control_t fcw0, fcw1; @@ -303,7 +303,7 @@ void test_double_arith(double (*tf)(double, double), _FPU_GETCW(fcw0); fcw1 = ((fcw0 & ~_FPU_EXTENDED) | _FPU_DOUBLE); _FPU_SETCW(fcw1); -#endif +#endif rr = (*rf)(x, y); #ifdef __i386__ _FPU_SETCW(fcw0); @@ -386,7 +386,7 @@ void test_float_int_conv(float x) printf("\n\ttrue = %d\n\tfalse = %d\n", rr, tr); } } - + void test_double_int_conv(double x) { int tr, rr; diff --git a/stdio-common/bug16.c b/stdio-common/bug16.c index 84269f3..1112c39 100644 --- a/stdio-common/bug16.c +++ b/stdio-common/bug16.c @@ -20,7 +20,7 @@ do_test (void) int ret = 0; for (size_t i = 0; i < sizeof (tests) / sizeof (tests[0]); ++i) - { + { snprintf (buf, sizeof (buf), "%.0LA", tests[i].val); size_t j; diff --git a/stdlib/random.c b/stdlib/random.c index 967dec3..0235ebe 100644 --- a/stdlib/random.c +++ b/stdlib/random.c @@ -24,7 +24,7 @@ /* Copyright (C) 1983 Regents of the University of California. All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,7 +37,7 @@ 4. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE diff --git a/sunrpc/rpcsvc/rquota.x b/sunrpc/rpcsvc/rquota.x index 62888f6..c457524 100644 --- a/sunrpc/rpcsvc/rquota.x +++ b/sunrpc/rpcsvc/rquota.x @@ -27,7 +27,7 @@ struct rquota { unsigned int rq_curfiles; /* current # allocated files */ unsigned int rq_btimeleft; /* time left for excessive disk use */ unsigned int rq_ftimeleft; /* time left for excessive files */ -}; +}; enum gqr_status { Q_OK = 1, /* quota returned */ diff --git a/sysdeps/ieee754/dbl-64/powtwo.tbl b/sysdeps/ieee754/dbl-64/powtwo.tbl index 4d0aa7a..2963d14 100644 --- a/sysdeps/ieee754/dbl-64/powtwo.tbl +++ b/sysdeps/ieee754/dbl-64/powtwo.tbl @@ -23,9 +23,9 @@ -static const double powtwo[] = { 1.0, 2.0, 4.0, - 8.0, 16.0, 32.0, 64.0, 128.0, - 256.0, 512.0, 1024.0, 2048.0, 4096.0, - 8192.0, 16384.0, 32768.0, 65536.0, 131072.0, - 262144.0, 524288.0, 1048576.0, 2097152.0, 4194304.0, - 8388608.0, 16777216.0, 33554432.0, 67108864.0, 134217728.0 }; +static const double powtwo[] = { 1.0, 2.0, 4.0, + 8.0, 16.0, 32.0, 64.0, 128.0, + 256.0, 512.0, 1024.0, 2048.0, 4096.0, + 8192.0, 16384.0, 32768.0, 65536.0, 131072.0, + 262144.0, 524288.0, 1048576.0, 2097152.0, 4194304.0, + 8388608.0, 16777216.0, 33554432.0, 67108864.0, 134217728.0 }; diff --git a/sysdeps/ieee754/flt-32/k_cosf.c b/sysdeps/ieee754/flt-32/k_cosf.c index fe4b453..63ca822 100644 --- a/sysdeps/ieee754/flt-32/k_cosf.c +++ b/sysdeps/ieee754/flt-32/k_cosf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ @@ -20,7 +20,7 @@ static char rcsid[] = "$NetBSD: k_cosf.c,v 1.4 1995/05/10 20:46:23 jtc Exp $"; #include <math.h> #include <math_private.h> -static const float +static const float one = 1.0000000000e+00, /* 0x3f800000 */ C1 = 4.1666667908e-02, /* 0x3d2aaaab */ C2 = -1.3888889225e-03, /* 0xbab60b61 */ @@ -40,7 +40,7 @@ float __kernel_cosf(float x, float y) } z = x*x; r = z*(C1+z*(C2+z*(C3+z*(C4+z*(C5+z*C6))))); - if(ix < 0x3e99999a) /* if |x| < 0.3 */ + if(ix < 0x3e99999a) /* if |x| < 0.3 */ return one - ((float)0.5*z - (z*r - x*y)); else { if(ix > 0x3f480000) { /* x > 0.78125 */ diff --git a/sysdeps/ieee754/flt-32/k_rem_pio2f.c b/sysdeps/ieee754/flt-32/k_rem_pio2f.c index e54a067..b19e5e0 100644 --- a/sysdeps/ieee754/flt-32/k_rem_pio2f.c +++ b/sysdeps/ieee754/flt-32/k_rem_pio2f.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ @@ -39,7 +39,7 @@ static const float PIo2[] = { 6.3331015649e-25, /* 0x17440000 */ }; -static const float +static const float zero = 0.0, one = 1.0, two8 = 2.5600000000e+02, /* 0x43800000 */ @@ -87,7 +87,7 @@ recompute: i = (iq[jz-1]>>(8-q0)); n += i; iq[jz-1] -= i<<(8-q0); ih = iq[jz-1]>>(7-q0); - } + } else if(q0==0) ih = iq[jz-1]>>7; else if(z>=(float)0.5) ih=2; @@ -138,7 +138,7 @@ recompute: while(iq[jz]==0) { jz--; q0-=8;} } else { /* break z into 8-bit if necessary */ z = __scalbnf(z,-q0); - if(z>=two8) { + if(z>=two8) { fw = (float)((int32_t)(twon8*z)); iq[jz] = (int32_t)(z-two8*fw); jz += 1; q0 += 8; @@ -163,7 +163,7 @@ recompute: case 0: fw = 0.0; for (i=jz;i>=0;i--) fw += fq[i]; - y[0] = (ih==0)? fw: -fw; + y[0] = (ih==0)? fw: -fw; break; case 1: case 2:; @@ -194,7 +194,7 @@ recompute: fq[i] += fq[i-1]-fv; fq[i-1] = fv; } - for (fw=0.0,i=jz;i>=2;i--) fw += fq[i]; + for (fw=0.0,i=jz;i>=2;i--) fw += fq[i]; if(ih==0) { y[0] = fq[0]; y[1] = fq[1]; y[2] = fw; } else { diff --git a/sysdeps/ieee754/flt-32/k_sinf.c b/sysdeps/ieee754/flt-32/k_sinf.c index e65fb98..0bafd83 100644 --- a/sysdeps/ieee754/flt-32/k_sinf.c +++ b/sysdeps/ieee754/flt-32/k_sinf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ @@ -20,7 +20,7 @@ static char rcsid[] = "$NetBSD: k_sinf.c,v 1.4 1995/05/10 20:46:33 jtc Exp $"; #include <math.h> #include <math_private.h> -static const float +static const float half = 5.0000000000e-01,/* 0x3f000000 */ S1 = -1.6666667163e-01, /* 0xbe2aaaab */ S2 = 8.3333337680e-03, /* 0x3c088889 */ diff --git a/sysdeps/ieee754/flt-32/k_tanf.c b/sysdeps/ieee754/flt-32/k_tanf.c index be9a5d0..d918826 100644 --- a/sysdeps/ieee754/flt-32/k_tanf.c +++ b/sysdeps/ieee754/flt-32/k_tanf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ @@ -19,7 +19,7 @@ static char rcsid[] = "$NetBSD: k_tanf.c,v 1.4 1995/05/10 20:46:39 jtc Exp $"; #include <math.h> #include <math_private.h> -static const float +static const float one = 1.0000000000e+00, /* 0x3f800000 */ pio4 = 7.8539812565e-01, /* 0x3f490fda */ pio4lo= 3.7748947079e-08, /* 0x33222168 */ @@ -76,7 +76,7 @@ float __kernel_tanf(float x, float y, int iy) return (float)(1-((hx>>30)&2))*(v-(float)2.0*(x-(w*w/(w+v)-r))); } if(iy==1) return w; - else { /* if allow error up to 2 ulp, + else { /* if allow error up to 2 ulp, simply return -1.0/(x+r) here */ /* compute -1.0/(x+r) accurately */ float a,t; diff --git a/sysdeps/ieee754/flt-32/s_atanf.c b/sysdeps/ieee754/flt-32/s_atanf.c index be7e674..02c5e46 100644 --- a/sysdeps/ieee754/flt-32/s_atanf.c +++ b/sysdeps/ieee754/flt-32/s_atanf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ @@ -73,9 +73,9 @@ float __atanf(float x) x = fabsf(x); if (ix < 0x3f980000) { /* |x| < 1.1875 */ if (ix < 0x3f300000) { /* 7/16 <=|x|<11/16 */ - id = 0; x = ((float)2.0*x-one)/((float)2.0+x); + id = 0; x = ((float)2.0*x-one)/((float)2.0+x); } else { /* 11/16<=|x|< 19/16 */ - id = 1; x = (x-one)/(x+one); + id = 1; x = (x-one)/(x+one); } } else { if (ix < 0x401c0000) { /* |x| < 2.4375 */ diff --git a/sysdeps/ieee754/flt-32/s_copysignf.c b/sysdeps/ieee754/flt-32/s_copysignf.c index 8bdf997..1621836 100644 --- a/sysdeps/ieee754/flt-32/s_copysignf.c +++ b/sysdeps/ieee754/flt-32/s_copysignf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ diff --git a/sysdeps/ieee754/flt-32/s_erff.c b/sysdeps/ieee754/flt-32/s_erff.c index 17eeca4..7d17f42 100644 --- a/sysdeps/ieee754/flt-32/s_erff.c +++ b/sysdeps/ieee754/flt-32/s_erff.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ @@ -43,7 +43,7 @@ qq3 = 5.0813062117e-03, /* 0x3ba68116 */ qq4 = 1.3249473704e-04, /* 0x390aee49 */ qq5 = -3.9602282413e-06, /* 0xb684e21a */ /* - * Coefficients for approximation to erf in [0.84375,1.25] + * Coefficients for approximation to erf in [0.84375,1.25] */ pa0 = -2.3621185683e-03, /* 0xbb1acdc6 */ pa1 = 4.1485610604e-01, /* 0x3ed46805 */ @@ -108,7 +108,7 @@ float __erff(float x) if(ix < 0x3f580000) { /* |x|<0.84375 */ if(ix < 0x31800000) { /* |x|<2**-28 */ - if (ix < 0x04000000) + if (ix < 0x04000000) /*avoid underflow */ return (float)0.125*((float)8.0*x+efx8*x); return x + efx*x; @@ -179,7 +179,7 @@ float __erfcf(float x) P = pa0+s*(pa1+s*(pa2+s*(pa3+s*(pa4+s*(pa5+s*pa6))))); Q = one+s*(qa1+s*(qa2+s*(qa3+s*(qa4+s*(qa5+s*qa6))))); if(hx>=0) { - z = one-erx; return z - P/Q; + z = one-erx; return z - P/Q; } else { z = erx+P/Q; return one+z; } diff --git a/sysdeps/ieee754/flt-32/s_fabsf.c b/sysdeps/ieee754/flt-32/s_fabsf.c index 6195265..c58aede 100644 --- a/sysdeps/ieee754/flt-32/s_fabsf.c +++ b/sysdeps/ieee754/flt-32/s_fabsf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ diff --git a/sysdeps/ieee754/flt-32/s_frexpf.c b/sysdeps/ieee754/flt-32/s_frexpf.c index abb8c0a..67a28d3 100644 --- a/sysdeps/ieee754/flt-32/s_frexpf.c +++ b/sysdeps/ieee754/flt-32/s_frexpf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ diff --git a/sysdeps/ieee754/flt-32/s_logbf.c b/sysdeps/ieee754/flt-32/s_logbf.c index e2b3aaa..011adbb 100644 --- a/sysdeps/ieee754/flt-32/s_logbf.c +++ b/sysdeps/ieee754/flt-32/s_logbf.c @@ -8,7 +8,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ diff --git a/sysdeps/ieee754/ldbl-128/e_rem_pio2l.c b/sysdeps/ieee754/ldbl-128/e_rem_pio2l.c index ee856ac..644afc4 100644 --- a/sysdeps/ieee754/ldbl-128/e_rem_pio2l.c +++ b/sysdeps/ieee754/ldbl-128/e_rem_pio2l.c @@ -21,166 +21,166 @@ #include <math_private.h> /* - * Table of constants for 2/pi, 5628 hexadecimal digits of 2/pi + * Table of constants for 2/pi, 5628 hexadecimal digits of 2/pi */ static const int32_t two_over_pi[] = { -0xa2f983, 0x6e4e44, 0x1529fc, 0x2757d1, 0xf534dd, 0xc0db62, -0x95993c, 0x439041, 0xfe5163, 0xabdebb, 0xc561b7, 0x246e3a, -0x424dd2, 0xe00649, 0x2eea09, 0xd1921c, 0xfe1deb, 0x1cb129, -0xa73ee8, 0x8235f5, 0x2ebb44, 0x84e99c, 0x7026b4, 0x5f7e41, -0x3991d6, 0x398353, 0x39f49c, 0x845f8b, 0xbdf928, 0x3b1ff8, -0x97ffde, 0x05980f, 0xef2f11, 0x8b5a0a, 0x6d1f6d, 0x367ecf, -0x27cb09, 0xb74f46, 0x3f669e, 0x5fea2d, 0x7527ba, 0xc7ebe5, -0xf17b3d, 0x0739f7, 0x8a5292, 0xea6bfb, 0x5fb11f, 0x8d5d08, -0x560330, 0x46fc7b, 0x6babf0, 0xcfbc20, 0x9af436, 0x1da9e3, -0x91615e, 0xe61b08, 0x659985, 0x5f14a0, 0x68408d, 0xffd880, -0x4d7327, 0x310606, 0x1556ca, 0x73a8c9, 0x60e27b, 0xc08c6b, -0x47c419, 0xc367cd, 0xdce809, 0x2a8359, 0xc4768b, 0x961ca6, -0xddaf44, 0xd15719, 0x053ea5, 0xff0705, 0x3f7e33, 0xe832c2, -0xde4f98, 0x327dbb, 0xc33d26, 0xef6b1e, 0x5ef89f, 0x3a1f35, -0xcaf27f, 0x1d87f1, 0x21907c, 0x7c246a, 0xfa6ed5, 0x772d30, -0x433b15, 0xc614b5, 0x9d19c3, 0xc2c4ad, 0x414d2c, 0x5d000c, -0x467d86, 0x2d71e3, 0x9ac69b, 0x006233, 0x7cd2b4, 0x97a7b4, -0xd55537, 0xf63ed7, 0x1810a3, 0xfc764d, 0x2a9d64, 0xabd770, -0xf87c63, 0x57b07a, 0xe71517, 0x5649c0, 0xd9d63b, 0x3884a7, -0xcb2324, 0x778ad6, 0x23545a, 0xb91f00, 0x1b0af1, 0xdfce19, -0xff319f, 0x6a1e66, 0x615799, 0x47fbac, 0xd87f7e, 0xb76522, -0x89e832, 0x60bfe6, 0xcdc4ef, 0x09366c, 0xd43f5d, 0xd7de16, -0xde3b58, 0x929bde, 0x2822d2, 0xe88628, 0x4d58e2, 0x32cac6, -0x16e308, 0xcb7de0, 0x50c017, 0xa71df3, 0x5be018, 0x34132e, -0x621283, 0x014883, 0x5b8ef5, 0x7fb0ad, 0xf2e91e, 0x434a48, -0xd36710, 0xd8ddaa, 0x425fae, 0xce616a, 0xa4280a, 0xb499d3, -0xf2a606, 0x7f775c, 0x83c2a3, 0x883c61, 0x78738a, 0x5a8caf, -0xbdd76f, 0x63a62d, 0xcbbff4, 0xef818d, 0x67c126, 0x45ca55, -0x36d9ca, 0xd2a828, 0x8d61c2, 0x77c912, 0x142604, 0x9b4612, -0xc459c4, 0x44c5c8, 0x91b24d, 0xf31700, 0xad43d4, 0xe54929, -0x10d5fd, 0xfcbe00, 0xcc941e, 0xeece70, 0xf53e13, 0x80f1ec, -0xc3e7b3, 0x28f8c7, 0x940593, 0x3e71c1, 0xb3092e, 0xf3450b, -0x9c1288, 0x7b20ab, 0x9fb52e, 0xc29247, 0x2f327b, 0x6d550c, -0x90a772, 0x1fe76b, 0x96cb31, 0x4a1679, 0xe27941, 0x89dff4, -0x9794e8, 0x84e6e2, 0x973199, 0x6bed88, 0x365f5f, 0x0efdbb, -0xb49a48, 0x6ca467, 0x427271, 0x325d8d, 0xb8159f, 0x09e5bc, -0x25318d, 0x3974f7, 0x1c0530, 0x010c0d, 0x68084b, 0x58ee2c, -0x90aa47, 0x02e774, 0x24d6bd, 0xa67df7, 0x72486e, 0xef169f, -0xa6948e, 0xf691b4, 0x5153d1, 0xf20acf, 0x339820, 0x7e4bf5, -0x6863b2, 0x5f3edd, 0x035d40, 0x7f8985, 0x295255, 0xc06437, -0x10d86d, 0x324832, 0x754c5b, 0xd4714e, 0x6e5445, 0xc1090b, -0x69f52a, 0xd56614, 0x9d0727, 0x50045d, 0xdb3bb4, 0xc576ea, -0x17f987, 0x7d6b49, 0xba271d, 0x296996, 0xacccc6, 0x5414ad, -0x6ae290, 0x89d988, 0x50722c, 0xbea404, 0x940777, 0x7030f3, -0x27fc00, 0xa871ea, 0x49c266, 0x3de064, 0x83dd97, 0x973fa3, -0xfd9443, 0x8c860d, 0xde4131, 0x9d3992, 0x8c70dd, 0xe7b717, -0x3bdf08, 0x2b3715, 0xa0805c, 0x93805a, 0x921110, 0xd8e80f, -0xaf806c, 0x4bffdb, 0x0f9038, 0x761859, 0x15a562, 0xbbcb61, -0xb989c7, 0xbd4010, 0x04f2d2, 0x277549, 0xf6b6eb, 0xbb22db, -0xaa140a, 0x2f2689, 0x768364, 0x333b09, 0x1a940e, 0xaa3a51, -0xc2a31d, 0xaeedaf, 0x12265c, 0x4dc26d, 0x9c7a2d, 0x9756c0, -0x833f03, 0xf6f009, 0x8c402b, 0x99316d, 0x07b439, 0x15200c, -0x5bc3d8, 0xc492f5, 0x4badc6, 0xa5ca4e, 0xcd37a7, 0x36a9e6, -0x9492ab, 0x6842dd, 0xde6319, 0xef8c76, 0x528b68, 0x37dbfc, -0xaba1ae, 0x3115df, 0xa1ae00, 0xdafb0c, 0x664d64, 0xb705ed, -0x306529, 0xbf5657, 0x3aff47, 0xb9f96a, 0xf3be75, 0xdf9328, -0x3080ab, 0xf68c66, 0x15cb04, 0x0622fa, 0x1de4d9, 0xa4b33d, -0x8f1b57, 0x09cd36, 0xe9424e, 0xa4be13, 0xb52333, 0x1aaaf0, -0xa8654f, 0xa5c1d2, 0x0f3f0b, 0xcd785b, 0x76f923, 0x048b7b, -0x721789, 0x53a6c6, 0xe26e6f, 0x00ebef, 0x584a9b, 0xb7dac4, -0xba66aa, 0xcfcf76, 0x1d02d1, 0x2df1b1, 0xc1998c, 0x77adc3, -0xda4886, 0xa05df7, 0xf480c6, 0x2ff0ac, 0x9aecdd, 0xbc5c3f, -0x6dded0, 0x1fc790, 0xb6db2a, 0x3a25a3, 0x9aaf00, 0x9353ad, -0x0457b6, 0xb42d29, 0x7e804b, 0xa707da, 0x0eaa76, 0xa1597b, -0x2a1216, 0x2db7dc, 0xfde5fa, 0xfedb89, 0xfdbe89, 0x6c76e4, -0xfca906, 0x70803e, 0x156e85, 0xff87fd, 0x073e28, 0x336761, -0x86182a, 0xeabd4d, 0xafe7b3, 0x6e6d8f, 0x396795, 0x5bbf31, -0x48d784, 0x16df30, 0x432dc7, 0x356125, 0xce70c9, 0xb8cb30, -0xfd6cbf, 0xa200a4, 0xe46c05, 0xa0dd5a, 0x476f21, 0xd21262, -0x845cb9, 0x496170, 0xe0566b, 0x015299, 0x375550, 0xb7d51e, -0xc4f133, 0x5f6e13, 0xe4305d, 0xa92e85, 0xc3b21d, 0x3632a1, -0xa4b708, 0xd4b1ea, 0x21f716, 0xe4698f, 0x77ff27, 0x80030c, -0x2d408d, 0xa0cd4f, 0x99a520, 0xd3a2b3, 0x0a5d2f, 0x42f9b4, -0xcbda11, 0xd0be7d, 0xc1db9b, 0xbd17ab, 0x81a2ca, 0x5c6a08, -0x17552e, 0x550027, 0xf0147f, 0x8607e1, 0x640b14, 0x8d4196, -0xdebe87, 0x2afdda, 0xb6256b, 0x34897b, 0xfef305, 0x9ebfb9, -0x4f6a68, 0xa82a4a, 0x5ac44f, 0xbcf82d, 0x985ad7, 0x95c7f4, -0x8d4d0d, 0xa63a20, 0x5f57a4, 0xb13f14, 0x953880, 0x0120cc, -0x86dd71, 0xb6dec9, 0xf560bf, 0x11654d, 0x6b0701, 0xacb08c, -0xd0c0b2, 0x485551, 0x0efb1e, 0xc37295, 0x3b06a3, 0x3540c0, -0x7bdc06, 0xcc45e0, 0xfa294e, 0xc8cad6, 0x41f3e8, 0xde647c, -0xd8649b, 0x31bed9, 0xc397a4, 0xd45877, 0xc5e369, 0x13daf0, -0x3c3aba, 0x461846, 0x5f7555, 0xf5bdd2, 0xc6926e, 0x5d2eac, -0xed440e, 0x423e1c, 0x87c461, 0xe9fd29, 0xf3d6e7, 0xca7c22, -0x35916f, 0xc5e008, 0x8dd7ff, 0xe26a6e, 0xc6fdb0, 0xc10893, -0x745d7c, 0xb2ad6b, 0x9d6ecd, 0x7b723e, 0x6a11c6, 0xa9cff7, -0xdf7329, 0xbac9b5, 0x5100b7, 0x0db2e2, 0x24ba74, 0x607de5, -0x8ad874, 0x2c150d, 0x0c1881, 0x94667e, 0x162901, 0x767a9f, -0xbefdfd, 0xef4556, 0x367ed9, 0x13d9ec, 0xb9ba8b, 0xfc97c4, -0x27a831, 0xc36ef1, 0x36c594, 0x56a8d8, 0xb5a8b4, 0x0ecccf, -0x2d8912, 0x34576f, 0x89562c, 0xe3ce99, 0xb920d6, 0xaa5e6b, -0x9c2a3e, 0xcc5f11, 0x4a0bfd, 0xfbf4e1, 0x6d3b8e, 0x2c86e2, -0x84d4e9, 0xa9b4fc, 0xd1eeef, 0xc9352e, 0x61392f, 0x442138, -0xc8d91b, 0x0afc81, 0x6a4afb, 0xd81c2f, 0x84b453, 0x8c994e, -0xcc2254, 0xdc552a, 0xd6c6c0, 0x96190b, 0xb8701a, 0x649569, -0x605a26, 0xee523f, 0x0f117f, 0x11b5f4, 0xf5cbfc, 0x2dbc34, -0xeebc34, 0xcc5de8, 0x605edd, 0x9b8e67, 0xef3392, 0xb817c9, -0x9b5861, 0xbc57e1, 0xc68351, 0x103ed8, 0x4871dd, 0xdd1c2d, -0xa118af, 0x462c21, 0xd7f359, 0x987ad9, 0xc0549e, 0xfa864f, -0xfc0656, 0xae79e5, 0x362289, 0x22ad38, 0xdc9367, 0xaae855, -0x382682, 0x9be7ca, 0xa40d51, 0xb13399, 0x0ed7a9, 0x480569, -0xf0b265, 0xa7887f, 0x974c88, 0x36d1f9, 0xb39221, 0x4a827b, -0x21cf98, 0xdc9f40, 0x5547dc, 0x3a74e1, 0x42eb67, 0xdf9dfe, -0x5fd45e, 0xa4677b, 0x7aacba, 0xa2f655, 0x23882b, 0x55ba41, -0x086e59, 0x862a21, 0x834739, 0xe6e389, 0xd49ee5, 0x40fb49, -0xe956ff, 0xca0f1c, 0x8a59c5, 0x2bfa94, 0xc5c1d3, 0xcfc50f, -0xae5adb, 0x86c547, 0x624385, 0x3b8621, 0x94792c, 0x876110, -0x7b4c2a, 0x1a2c80, 0x12bf43, 0x902688, 0x893c78, 0xe4c4a8, -0x7bdbe5, 0xc23ac4, 0xeaf426, 0x8a67f7, 0xbf920d, 0x2ba365, -0xb1933d, 0x0b7cbd, 0xdc51a4, 0x63dd27, 0xdde169, 0x19949a, -0x9529a8, 0x28ce68, 0xb4ed09, 0x209f44, 0xca984e, 0x638270, -0x237c7e, 0x32b90f, 0x8ef5a7, 0xe75614, 0x08f121, 0x2a9db5, -0x4d7e6f, 0x5119a5, 0xabf9b5, 0xd6df82, 0x61dd96, 0x023616, -0x9f3ac4, 0xa1a283, 0x6ded72, 0x7a8d39, 0xa9b882, 0x5c326b, -0x5b2746, 0xed3400, 0x7700d2, 0x55f4fc, 0x4d5901, 0x8071e0, -0xe13f89, 0xb295f3, 0x64a8f1, 0xaea74b, 0x38fc4c, 0xeab2bb, -0x47270b, 0xabc3a7, 0x34ba60, 0x52dd34, 0xf8563a, 0xeb7e8a, -0x31bb36, 0x5895b7, 0x47f7a9, 0x94c3aa, 0xd39225, 0x1e7f3e, -0xd8974e, 0xbba94f, 0xd8ae01, 0xe661b4, 0x393d8e, 0xa523aa, -0x33068e, 0x1633b5, 0x3bb188, 0x1d3a9d, 0x4013d0, 0xcc1be5, -0xf862e7, 0x3bf28f, 0x39b5bf, 0x0bc235, 0x22747e, 0xa247c0, -0xd52d1f, 0x19add3, 0x9094df, 0x9311d0, 0xb42b25, 0x496db2, -0xe264b2, 0x5ef135, 0x3bc6a4, 0x1a4ad0, 0xaac92e, 0x64e886, -0x573091, 0x982cfb, 0x311b1a, 0x08728b, 0xbdcee1, 0x60e142, -0xeb641d, 0xd0bba3, 0xe559d4, 0x597b8c, 0x2a4483, 0xf332ba, -0xf84867, 0x2c8d1b, 0x2fa9b0, 0x50f3dd, 0xf9f573, 0xdb61b4, -0xfe233e, 0x6c41a6, 0xeea318, 0x775a26, 0xbc5e5c, 0xcea708, -0x94dc57, 0xe20196, 0xf1e839, 0xbe4851, 0x5d2d2f, 0x4e9555, -0xd96ec2, 0xe7d755, 0x6304e0, 0xc02e0e, 0xfc40a0, 0xbbf9b3, -0x7125a7, 0x222dfb, 0xf619d8, 0x838c1c, 0x6619e6, 0xb20d55, -0xbb5137, 0x79e809, 0xaf9149, 0x0d73de, 0x0b0da5, 0xce7f58, -0xac1934, 0x724667, 0x7a1a13, 0x9e26bc, 0x4555e7, 0x585cb5, -0x711d14, 0x486991, 0x480d60, 0x56adab, 0xd62f64, 0x96ee0c, -0x212ff3, 0x5d6d88, 0xa67684, 0x95651e, 0xab9e0a, 0x4ddefe, -0x571010, 0x836a39, 0xf8ea31, 0x9e381d, 0xeac8b1, 0xcac96b, -0x37f21e, 0xd505e9, 0x984743, 0x9fc56c, 0x0331b7, 0x3b8bf8, -0x86e56a, 0x8dc343, 0x6230e7, 0x93cfd5, 0x6a8f2d, 0x733005, -0x1af021, 0xa09fcb, 0x7415a1, 0xd56b23, 0x6ff725, 0x2f4bc7, -0xb8a591, 0x7fac59, 0x5c55de, 0x212c38, 0xb13296, 0x5cff50, -0x366262, 0xfa7b16, 0xf4d9a6, 0x2acfe7, 0xf07403, 0xd4d604, -0x6fd916, 0x31b1bf, 0xcbb450, 0x5bd7c8, 0x0ce194, 0x6bd643, -0x4fd91c, 0xdf4543, 0x5f3453, 0xe2b5aa, 0xc9aec8, 0x131485, -0xf9d2bf, 0xbadb9e, 0x76f5b9, 0xaf15cf, 0xca3182, 0x14b56d, -0xe9fe4d, 0x50fc35, 0xf5aed5, 0xa2d0c1, 0xc96057, 0x192eb6, -0xe91d92, 0x07d144, 0xaea3c6, 0x343566, 0x26d5b4, 0x3161e2, -0x37f1a2, 0x209eff, 0x958e23, 0x493798, 0x35f4a6, 0x4bdc02, -0xc2be13, 0xbe80a0, 0x0b72a3, 0x115c5f, 0x1e1bd1, 0x0db4d3, -0x869e85, 0x96976b, 0x2ac91f, 0x8a26c2, 0x3070f0, 0x041412, -0xfc9fa5, 0xf72a38, 0x9c6878, 0xe2aa76, 0x50cfe1, 0x559274, -0x934e38, 0x0a92f7, 0x5533f0, 0xa63db4, 0x399971, 0xe2b755, -0xa98a7c, 0x008f19, 0xac54d2, 0x2ea0b4, 0xf5f3e0, 0x60c849, -0xffd269, 0xae52ce, 0x7a5fdd, 0xe9ce06, 0xfb0ae8, 0xa50cce, -0xea9d3e, 0x3766dd, 0xb834f5, 0x0da090, 0x846f88, 0x4ae3d5, -0x099a03, 0x2eae2d, 0xfcb40a, 0xfb9b33, 0xe281dd, 0x1b16ba, -0xd8c0af, 0xd96b97, 0xb52dc9, 0x9c277f, 0x5951d5, 0x21ccd6, -0xb6496b, 0x584562, 0xb3baf2, 0xa1a5c4, 0x7ca2cf, 0xa9b93d, -0x7b7b89, 0x483d38, +0xa2f983, 0x6e4e44, 0x1529fc, 0x2757d1, 0xf534dd, 0xc0db62, +0x95993c, 0x439041, 0xfe5163, 0xabdebb, 0xc561b7, 0x246e3a, +0x424dd2, 0xe00649, 0x2eea09, 0xd1921c, 0xfe1deb, 0x1cb129, +0xa73ee8, 0x8235f5, 0x2ebb44, 0x84e99c, 0x7026b4, 0x5f7e41, +0x3991d6, 0x398353, 0x39f49c, 0x845f8b, 0xbdf928, 0x3b1ff8, +0x97ffde, 0x05980f, 0xef2f11, 0x8b5a0a, 0x6d1f6d, 0x367ecf, +0x27cb09, 0xb74f46, 0x3f669e, 0x5fea2d, 0x7527ba, 0xc7ebe5, +0xf17b3d, 0x0739f7, 0x8a5292, 0xea6bfb, 0x5fb11f, 0x8d5d08, +0x560330, 0x46fc7b, 0x6babf0, 0xcfbc20, 0x9af436, 0x1da9e3, +0x91615e, 0xe61b08, 0x659985, 0x5f14a0, 0x68408d, 0xffd880, +0x4d7327, 0x310606, 0x1556ca, 0x73a8c9, 0x60e27b, 0xc08c6b, +0x47c419, 0xc367cd, 0xdce809, 0x2a8359, 0xc4768b, 0x961ca6, +0xddaf44, 0xd15719, 0x053ea5, 0xff0705, 0x3f7e33, 0xe832c2, +0xde4f98, 0x327dbb, 0xc33d26, 0xef6b1e, 0x5ef89f, 0x3a1f35, +0xcaf27f, 0x1d87f1, 0x21907c, 0x7c246a, 0xfa6ed5, 0x772d30, +0x433b15, 0xc614b5, 0x9d19c3, 0xc2c4ad, 0x414d2c, 0x5d000c, +0x467d86, 0x2d71e3, 0x9ac69b, 0x006233, 0x7cd2b4, 0x97a7b4, +0xd55537, 0xf63ed7, 0x1810a3, 0xfc764d, 0x2a9d64, 0xabd770, +0xf87c63, 0x57b07a, 0xe71517, 0x5649c0, 0xd9d63b, 0x3884a7, +0xcb2324, 0x778ad6, 0x23545a, 0xb91f00, 0x1b0af1, 0xdfce19, +0xff319f, 0x6a1e66, 0x615799, 0x47fbac, 0xd87f7e, 0xb76522, +0x89e832, 0x60bfe6, 0xcdc4ef, 0x09366c, 0xd43f5d, 0xd7de16, +0xde3b58, 0x929bde, 0x2822d2, 0xe88628, 0x4d58e2, 0x32cac6, +0x16e308, 0xcb7de0, 0x50c017, 0xa71df3, 0x5be018, 0x34132e, +0x621283, 0x014883, 0x5b8ef5, 0x7fb0ad, 0xf2e91e, 0x434a48, +0xd36710, 0xd8ddaa, 0x425fae, 0xce616a, 0xa4280a, 0xb499d3, +0xf2a606, 0x7f775c, 0x83c2a3, 0x883c61, 0x78738a, 0x5a8caf, +0xbdd76f, 0x63a62d, 0xcbbff4, 0xef818d, 0x67c126, 0x45ca55, +0x36d9ca, 0xd2a828, 0x8d61c2, 0x77c912, 0x142604, 0x9b4612, +0xc459c4, 0x44c5c8, 0x91b24d, 0xf31700, 0xad43d4, 0xe54929, +0x10d5fd, 0xfcbe00, 0xcc941e, 0xeece70, 0xf53e13, 0x80f1ec, +0xc3e7b3, 0x28f8c7, 0x940593, 0x3e71c1, 0xb3092e, 0xf3450b, +0x9c1288, 0x7b20ab, 0x9fb52e, 0xc29247, 0x2f327b, 0x6d550c, +0x90a772, 0x1fe76b, 0x96cb31, 0x4a1679, 0xe27941, 0x89dff4, +0x9794e8, 0x84e6e2, 0x973199, 0x6bed88, 0x365f5f, 0x0efdbb, +0xb49a48, 0x6ca467, 0x427271, 0x325d8d, 0xb8159f, 0x09e5bc, +0x25318d, 0x3974f7, 0x1c0530, 0x010c0d, 0x68084b, 0x58ee2c, +0x90aa47, 0x02e774, 0x24d6bd, 0xa67df7, 0x72486e, 0xef169f, +0xa6948e, 0xf691b4, 0x5153d1, 0xf20acf, 0x339820, 0x7e4bf5, +0x6863b2, 0x5f3edd, 0x035d40, 0x7f8985, 0x295255, 0xc06437, +0x10d86d, 0x324832, 0x754c5b, 0xd4714e, 0x6e5445, 0xc1090b, +0x69f52a, 0xd56614, 0x9d0727, 0x50045d, 0xdb3bb4, 0xc576ea, +0x17f987, 0x7d6b49, 0xba271d, 0x296996, 0xacccc6, 0x5414ad, +0x6ae290, 0x89d988, 0x50722c, 0xbea404, 0x940777, 0x7030f3, +0x27fc00, 0xa871ea, 0x49c266, 0x3de064, 0x83dd97, 0x973fa3, +0xfd9443, 0x8c860d, 0xde4131, 0x9d3992, 0x8c70dd, 0xe7b717, +0x3bdf08, 0x2b3715, 0xa0805c, 0x93805a, 0x921110, 0xd8e80f, +0xaf806c, 0x4bffdb, 0x0f9038, 0x761859, 0x15a562, 0xbbcb61, +0xb989c7, 0xbd4010, 0x04f2d2, 0x277549, 0xf6b6eb, 0xbb22db, +0xaa140a, 0x2f2689, 0x768364, 0x333b09, 0x1a940e, 0xaa3a51, +0xc2a31d, 0xaeedaf, 0x12265c, 0x4dc26d, 0x9c7a2d, 0x9756c0, +0x833f03, 0xf6f009, 0x8c402b, 0x99316d, 0x07b439, 0x15200c, +0x5bc3d8, 0xc492f5, 0x4badc6, 0xa5ca4e, 0xcd37a7, 0x36a9e6, +0x9492ab, 0x6842dd, 0xde6319, 0xef8c76, 0x528b68, 0x37dbfc, +0xaba1ae, 0x3115df, 0xa1ae00, 0xdafb0c, 0x664d64, 0xb705ed, +0x306529, 0xbf5657, 0x3aff47, 0xb9f96a, 0xf3be75, 0xdf9328, +0x3080ab, 0xf68c66, 0x15cb04, 0x0622fa, 0x1de4d9, 0xa4b33d, +0x8f1b57, 0x09cd36, 0xe9424e, 0xa4be13, 0xb52333, 0x1aaaf0, +0xa8654f, 0xa5c1d2, 0x0f3f0b, 0xcd785b, 0x76f923, 0x048b7b, +0x721789, 0x53a6c6, 0xe26e6f, 0x00ebef, 0x584a9b, 0xb7dac4, +0xba66aa, 0xcfcf76, 0x1d02d1, 0x2df1b1, 0xc1998c, 0x77adc3, +0xda4886, 0xa05df7, 0xf480c6, 0x2ff0ac, 0x9aecdd, 0xbc5c3f, +0x6dded0, 0x1fc790, 0xb6db2a, 0x3a25a3, 0x9aaf00, 0x9353ad, +0x0457b6, 0xb42d29, 0x7e804b, 0xa707da, 0x0eaa76, 0xa1597b, +0x2a1216, 0x2db7dc, 0xfde5fa, 0xfedb89, 0xfdbe89, 0x6c76e4, +0xfca906, 0x70803e, 0x156e85, 0xff87fd, 0x073e28, 0x336761, +0x86182a, 0xeabd4d, 0xafe7b3, 0x6e6d8f, 0x396795, 0x5bbf31, +0x48d784, 0x16df30, 0x432dc7, 0x356125, 0xce70c9, 0xb8cb30, +0xfd6cbf, 0xa200a4, 0xe46c05, 0xa0dd5a, 0x476f21, 0xd21262, +0x845cb9, 0x496170, 0xe0566b, 0x015299, 0x375550, 0xb7d51e, +0xc4f133, 0x5f6e13, 0xe4305d, 0xa92e85, 0xc3b21d, 0x3632a1, +0xa4b708, 0xd4b1ea, 0x21f716, 0xe4698f, 0x77ff27, 0x80030c, +0x2d408d, 0xa0cd4f, 0x99a520, 0xd3a2b3, 0x0a5d2f, 0x42f9b4, +0xcbda11, 0xd0be7d, 0xc1db9b, 0xbd17ab, 0x81a2ca, 0x5c6a08, +0x17552e, 0x550027, 0xf0147f, 0x8607e1, 0x640b14, 0x8d4196, +0xdebe87, 0x2afdda, 0xb6256b, 0x34897b, 0xfef305, 0x9ebfb9, +0x4f6a68, 0xa82a4a, 0x5ac44f, 0xbcf82d, 0x985ad7, 0x95c7f4, +0x8d4d0d, 0xa63a20, 0x5f57a4, 0xb13f14, 0x953880, 0x0120cc, +0x86dd71, 0xb6dec9, 0xf560bf, 0x11654d, 0x6b0701, 0xacb08c, +0xd0c0b2, 0x485551, 0x0efb1e, 0xc37295, 0x3b06a3, 0x3540c0, +0x7bdc06, 0xcc45e0, 0xfa294e, 0xc8cad6, 0x41f3e8, 0xde647c, +0xd8649b, 0x31bed9, 0xc397a4, 0xd45877, 0xc5e369, 0x13daf0, +0x3c3aba, 0x461846, 0x5f7555, 0xf5bdd2, 0xc6926e, 0x5d2eac, +0xed440e, 0x423e1c, 0x87c461, 0xe9fd29, 0xf3d6e7, 0xca7c22, +0x35916f, 0xc5e008, 0x8dd7ff, 0xe26a6e, 0xc6fdb0, 0xc10893, +0x745d7c, 0xb2ad6b, 0x9d6ecd, 0x7b723e, 0x6a11c6, 0xa9cff7, +0xdf7329, 0xbac9b5, 0x5100b7, 0x0db2e2, 0x24ba74, 0x607de5, +0x8ad874, 0x2c150d, 0x0c1881, 0x94667e, 0x162901, 0x767a9f, +0xbefdfd, 0xef4556, 0x367ed9, 0x13d9ec, 0xb9ba8b, 0xfc97c4, +0x27a831, 0xc36ef1, 0x36c594, 0x56a8d8, 0xb5a8b4, 0x0ecccf, +0x2d8912, 0x34576f, 0x89562c, 0xe3ce99, 0xb920d6, 0xaa5e6b, +0x9c2a3e, 0xcc5f11, 0x4a0bfd, 0xfbf4e1, 0x6d3b8e, 0x2c86e2, +0x84d4e9, 0xa9b4fc, 0xd1eeef, 0xc9352e, 0x61392f, 0x442138, +0xc8d91b, 0x0afc81, 0x6a4afb, 0xd81c2f, 0x84b453, 0x8c994e, +0xcc2254, 0xdc552a, 0xd6c6c0, 0x96190b, 0xb8701a, 0x649569, +0x605a26, 0xee523f, 0x0f117f, 0x11b5f4, 0xf5cbfc, 0x2dbc34, +0xeebc34, 0xcc5de8, 0x605edd, 0x9b8e67, 0xef3392, 0xb817c9, +0x9b5861, 0xbc57e1, 0xc68351, 0x103ed8, 0x4871dd, 0xdd1c2d, +0xa118af, 0x462c21, 0xd7f359, 0x987ad9, 0xc0549e, 0xfa864f, +0xfc0656, 0xae79e5, 0x362289, 0x22ad38, 0xdc9367, 0xaae855, +0x382682, 0x9be7ca, 0xa40d51, 0xb13399, 0x0ed7a9, 0x480569, +0xf0b265, 0xa7887f, 0x974c88, 0x36d1f9, 0xb39221, 0x4a827b, +0x21cf98, 0xdc9f40, 0x5547dc, 0x3a74e1, 0x42eb67, 0xdf9dfe, +0x5fd45e, 0xa4677b, 0x7aacba, 0xa2f655, 0x23882b, 0x55ba41, +0x086e59, 0x862a21, 0x834739, 0xe6e389, 0xd49ee5, 0x40fb49, +0xe956ff, 0xca0f1c, 0x8a59c5, 0x2bfa94, 0xc5c1d3, 0xcfc50f, +0xae5adb, 0x86c547, 0x624385, 0x3b8621, 0x94792c, 0x876110, +0x7b4c2a, 0x1a2c80, 0x12bf43, 0x902688, 0x893c78, 0xe4c4a8, +0x7bdbe5, 0xc23ac4, 0xeaf426, 0x8a67f7, 0xbf920d, 0x2ba365, +0xb1933d, 0x0b7cbd, 0xdc51a4, 0x63dd27, 0xdde169, 0x19949a, +0x9529a8, 0x28ce68, 0xb4ed09, 0x209f44, 0xca984e, 0x638270, +0x237c7e, 0x32b90f, 0x8ef5a7, 0xe75614, 0x08f121, 0x2a9db5, +0x4d7e6f, 0x5119a5, 0xabf9b5, 0xd6df82, 0x61dd96, 0x023616, +0x9f3ac4, 0xa1a283, 0x6ded72, 0x7a8d39, 0xa9b882, 0x5c326b, +0x5b2746, 0xed3400, 0x7700d2, 0x55f4fc, 0x4d5901, 0x8071e0, +0xe13f89, 0xb295f3, 0x64a8f1, 0xaea74b, 0x38fc4c, 0xeab2bb, +0x47270b, 0xabc3a7, 0x34ba60, 0x52dd34, 0xf8563a, 0xeb7e8a, +0x31bb36, 0x5895b7, 0x47f7a9, 0x94c3aa, 0xd39225, 0x1e7f3e, +0xd8974e, 0xbba94f, 0xd8ae01, 0xe661b4, 0x393d8e, 0xa523aa, +0x33068e, 0x1633b5, 0x3bb188, 0x1d3a9d, 0x4013d0, 0xcc1be5, +0xf862e7, 0x3bf28f, 0x39b5bf, 0x0bc235, 0x22747e, 0xa247c0, +0xd52d1f, 0x19add3, 0x9094df, 0x9311d0, 0xb42b25, 0x496db2, +0xe264b2, 0x5ef135, 0x3bc6a4, 0x1a4ad0, 0xaac92e, 0x64e886, +0x573091, 0x982cfb, 0x311b1a, 0x08728b, 0xbdcee1, 0x60e142, +0xeb641d, 0xd0bba3, 0xe559d4, 0x597b8c, 0x2a4483, 0xf332ba, +0xf84867, 0x2c8d1b, 0x2fa9b0, 0x50f3dd, 0xf9f573, 0xdb61b4, +0xfe233e, 0x6c41a6, 0xeea318, 0x775a26, 0xbc5e5c, 0xcea708, +0x94dc57, 0xe20196, 0xf1e839, 0xbe4851, 0x5d2d2f, 0x4e9555, +0xd96ec2, 0xe7d755, 0x6304e0, 0xc02e0e, 0xfc40a0, 0xbbf9b3, +0x7125a7, 0x222dfb, 0xf619d8, 0x838c1c, 0x6619e6, 0xb20d55, +0xbb5137, 0x79e809, 0xaf9149, 0x0d73de, 0x0b0da5, 0xce7f58, +0xac1934, 0x724667, 0x7a1a13, 0x9e26bc, 0x4555e7, 0x585cb5, +0x711d14, 0x486991, 0x480d60, 0x56adab, 0xd62f64, 0x96ee0c, +0x212ff3, 0x5d6d88, 0xa67684, 0x95651e, 0xab9e0a, 0x4ddefe, +0x571010, 0x836a39, 0xf8ea31, 0x9e381d, 0xeac8b1, 0xcac96b, +0x37f21e, 0xd505e9, 0x984743, 0x9fc56c, 0x0331b7, 0x3b8bf8, +0x86e56a, 0x8dc343, 0x6230e7, 0x93cfd5, 0x6a8f2d, 0x733005, +0x1af021, 0xa09fcb, 0x7415a1, 0xd56b23, 0x6ff725, 0x2f4bc7, +0xb8a591, 0x7fac59, 0x5c55de, 0x212c38, 0xb13296, 0x5cff50, +0x366262, 0xfa7b16, 0xf4d9a6, 0x2acfe7, 0xf07403, 0xd4d604, +0x6fd916, 0x31b1bf, 0xcbb450, 0x5bd7c8, 0x0ce194, 0x6bd643, +0x4fd91c, 0xdf4543, 0x5f3453, 0xe2b5aa, 0xc9aec8, 0x131485, +0xf9d2bf, 0xbadb9e, 0x76f5b9, 0xaf15cf, 0xca3182, 0x14b56d, +0xe9fe4d, 0x50fc35, 0xf5aed5, 0xa2d0c1, 0xc96057, 0x192eb6, +0xe91d92, 0x07d144, 0xaea3c6, 0x343566, 0x26d5b4, 0x3161e2, +0x37f1a2, 0x209eff, 0x958e23, 0x493798, 0x35f4a6, 0x4bdc02, +0xc2be13, 0xbe80a0, 0x0b72a3, 0x115c5f, 0x1e1bd1, 0x0db4d3, +0x869e85, 0x96976b, 0x2ac91f, 0x8a26c2, 0x3070f0, 0x041412, +0xfc9fa5, 0xf72a38, 0x9c6878, 0xe2aa76, 0x50cfe1, 0x559274, +0x934e38, 0x0a92f7, 0x5533f0, 0xa63db4, 0x399971, 0xe2b755, +0xa98a7c, 0x008f19, 0xac54d2, 0x2ea0b4, 0xf5f3e0, 0x60c849, +0xffd269, 0xae52ce, 0x7a5fdd, 0xe9ce06, 0xfb0ae8, 0xa50cce, +0xea9d3e, 0x3766dd, 0xb834f5, 0x0da090, 0x846f88, 0x4ae3d5, +0x099a03, 0x2eae2d, 0xfcb40a, 0xfb9b33, 0xe281dd, 0x1b16ba, +0xd8c0af, 0xd96b97, 0xb52dc9, 0x9c277f, 0x5951d5, 0x21ccd6, +0xb6496b, 0x584562, 0xb3baf2, 0xa1a5c4, 0x7ca2cf, 0xa9b93d, +0x7b7b89, 0x483d38, }; static const long double c[] = { @@ -212,7 +212,7 @@ int32_t __ieee754_rem_pio2l(long double x, long double *y) if (ix < 0x40002d97c7f3321dLL) /* |x| in <pi/4, 3pi/4) */ { if (hx > 0) - { + { /* 113 + 113 bit PI is ok */ z = x - PI_2_1; y[0] = z - PI_2_1t; diff --git a/sysdeps/ieee754/ldbl-128/k_tanl.c b/sysdeps/ieee754/ldbl-128/k_tanl.c index cb2e947..140ce95 100644 --- a/sysdeps/ieee754/ldbl-128/k_tanl.c +++ b/sysdeps/ieee754/ldbl-128/k_tanl.c @@ -12,9 +12,9 @@ /* Long double expansions are Copyright (C) 2001 Stephen L. Moshier <moshier@na-net.ornl.gov> - and are incorporated herein by permission of the author. The author + and are incorporated herein by permission of the author. The author reserves the right to distribute this material elsewhere under different - copying permissions. These modifications are distributed here under + copying permissions. These modifications are distributed here under the following terms: This library is free software; you can redistribute it and/or diff --git a/sysdeps/ieee754/ldbl-128/s_atanl.c b/sysdeps/ieee754/ldbl-128/s_atanl.c index adac0a7..dc5e7ef 100644 --- a/sysdeps/ieee754/ldbl-128/s_atanl.c +++ b/sysdeps/ieee754/ldbl-128/s_atanl.c @@ -42,7 +42,7 @@ * */ -/* Copyright 2001 by Stephen L. Moshier <moshier@na-net.ornl.gov> +/* Copyright 2001 by Stephen L. Moshier <moshier@na-net.ornl.gov> This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public diff --git a/sysdeps/ieee754/ldbl-128/s_erfl.c b/sysdeps/ieee754/ldbl-128/s_erfl.c index 85c6356..d9d4195 100644 --- a/sysdeps/ieee754/ldbl-128/s_erfl.c +++ b/sysdeps/ieee754/ldbl-128/s_erfl.c @@ -11,9 +11,9 @@ /* Modifications and expansions for 128-bit long double are Copyright (C) 2001 Stephen L. Moshier <moshier@na-net.ornl.gov> - and are incorporated herein by permission of the author. The author + and are incorporated herein by permission of the author. The author reserves the right to distribute this material elsewhere under different - copying permissions. These modifications are distributed here under + copying permissions. These modifications are distributed here under the following terms: This library is free software; you can redistribute it and/or diff --git a/sysdeps/ieee754/ldbl-128/s_expm1l.c b/sysdeps/ieee754/ldbl-128/s_expm1l.c index ea63501..1c12109 100644 --- a/sysdeps/ieee754/ldbl-128/s_expm1l.c +++ b/sysdeps/ieee754/ldbl-128/s_expm1l.c @@ -35,7 +35,7 @@ * */ -/* Copyright 2001 by Stephen L. Moshier +/* Copyright 2001 by Stephen L. Moshier This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public diff --git a/sysdeps/ieee754/ldbl-128/s_log1pl.c b/sysdeps/ieee754/ldbl-128/s_log1pl.c index fad18e9..d991e8a 100644 --- a/sysdeps/ieee754/ldbl-128/s_log1pl.c +++ b/sysdeps/ieee754/ldbl-128/s_log1pl.c @@ -36,7 +36,7 @@ * IEEE -1, 8 100000 1.9e-34 4.3e-35 */ -/* Copyright 2001 by Stephen L. Moshier +/* Copyright 2001 by Stephen L. Moshier This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public diff --git a/sysdeps/ieee754/ldbl-128/s_nexttowardf.c b/sysdeps/ieee754/ldbl-128/s_nexttowardf.c index 02a1407..ccd49d2 100644 --- a/sysdeps/ieee754/ldbl-128/s_nexttowardf.c +++ b/sysdeps/ieee754/ldbl-128/s_nexttowardf.c @@ -26,7 +26,7 @@ float __nexttowardf(float x, long double y) int32_t hx,ix; int64_t hy,iy; u_int64_t ly; - + GET_FLOAT_WORD(hx,x); GET_LDOUBLE_WORDS64(hy,ly,y); ix = hx&0x7fffffff; /* |x| */ diff --git a/sysdeps/ieee754/ldbl-128/s_remquol.c b/sysdeps/ieee754/ldbl-128/s_remquol.c index c0f8d36..f916b64 100644 --- a/sysdeps/ieee754/ldbl-128/s_remquol.c +++ b/sysdeps/ieee754/ldbl-128/s_remquol.c @@ -50,7 +50,7 @@ __remquol (long double x, long double y, int *quo) if (hy <= 0x7ffbffffffffffffLL) x = __ieee754_fmodl (x, 8 * y); /* now x < 8y */ - + if (((hx - hy) | (lx - ly)) == 0) { *quo = qs ? -1 : 1; diff --git a/sysdeps/ieee754/ldbl-128/s_scalblnl.c b/sysdeps/ieee754/ldbl-128/s_scalblnl.c index f0df2da..f552393 100644 --- a/sysdeps/ieee754/ldbl-128/s_scalblnl.c +++ b/sysdeps/ieee754/ldbl-128/s_scalblnl.c @@ -1,7 +1,7 @@ /* s_scalblnl.c -- long double version of s_scalbn.c. * Conversion to IEEE quad long double by Jakub Jelinek, jj@ultra.linux.cz. */ - + /* @(#)s_scalbn.c 5.1 93/09/24 */ /* * ==================================================== diff --git a/sysdeps/ieee754/ldbl-128/s_scalbnl.c b/sysdeps/ieee754/ldbl-128/s_scalbnl.c index a14848d..8916dcbfd 100644 --- a/sysdeps/ieee754/ldbl-128/s_scalbnl.c +++ b/sysdeps/ieee754/ldbl-128/s_scalbnl.c @@ -1,7 +1,7 @@ /* s_scalbnl.c -- long double version of s_scalbn.c. * Conversion to IEEE quad long double by Jakub Jelinek, jj@ultra.linux.cz. */ - + /* @(#)s_scalbn.c 5.1 93/09/24 */ /* * ==================================================== diff --git a/sysdeps/ieee754/ldbl-128/s_tanl.c b/sysdeps/ieee754/ldbl-128/s_tanl.c index c4bb8c8..c7d6374 100644 --- a/sysdeps/ieee754/ldbl-128/s_tanl.c +++ b/sysdeps/ieee754/ldbl-128/s_tanl.c @@ -1,7 +1,7 @@ /* s_tanl.c -- long double version of s_tan.c. * Conversion to IEEE quad long double by Jakub Jelinek, jj@ultra.linux.cz. */ - + /* @(#)s_tan.c 5.1 93/09/24 */ /* * ==================================================== diff --git a/sysdeps/ieee754/ldbl-128/t_sincosl.c b/sysdeps/ieee754/ldbl-128/t_sincosl.c index e6c2318..95fe01e 100644 --- a/sysdeps/ieee754/ldbl-128/t_sincosl.c +++ b/sysdeps/ieee754/ldbl-128/t_sincosl.c @@ -34,7 +34,7 @@ const long double __sincosl_table[] = { /* sin(x) = 0.25dc50bc95711d0d9787d108fd438cf5959ee0bfb7a1e36e8b1a112968f356657420e9cc9ea */ 1.47892995873409608580026675734609314e-01L, /* 3ffc2ee285e4ab88e86cbc3e8847ea1c */ 9.74950446464233268291647449768590886e-36L, /* 3f8a9eb2b3dc17f6f43c6dd16342252d */ - + /* x = 1.56250000000000000000000000000000000e-01 3ffc4000000000000000000000000000 */ /* cos(x) = 0.fce1a053e621438b6d60c76e8c45bf0a9dc71aa16f922acc10e95144ec796a249813c9cb649 */ 9.87817783816471944100503034363211317e-01L, /* 3ffef9c340a7cc428716dac18edd188b */ diff --git a/sysdeps/ieee754/ldbl-128ibm/k_cosl.c b/sysdeps/ieee754/ldbl-128ibm/k_cosl.c index 2a241fd..0b81782 100644 --- a/sysdeps/ieee754/ldbl-128ibm/k_cosl.c +++ b/sysdeps/ieee754/ldbl-128ibm/k_cosl.c @@ -120,7 +120,7 @@ __kernel_cosl(long double x, long double y) The following should work for double but generates the wrong index. For now the code above converts double to ieee extended to compute the index back to double for the h value. - + index = 0x3fe - (tix >> 20); hix = (tix + (0x200 << index)) & (0xfffffc00 << index); if (signbit (x)) diff --git a/sysdeps/ieee754/ldbl-128ibm/k_sincosl.c b/sysdeps/ieee754/ldbl-128ibm/k_sincosl.c index 4958077..fc1ead6 100644 --- a/sysdeps/ieee754/ldbl-128ibm/k_sincosl.c +++ b/sysdeps/ieee754/ldbl-128ibm/k_sincosl.c @@ -146,8 +146,8 @@ __kernel_sincosl(long double x, long double y, long double *sinx, long double *c /* The following should work for double but generates the wrong index. For now the code above converts double to ieee extended to compute - the index back to double for the h value. - + the index back to double for the h value. + index = 0x3fe - (tix >> 20); hix = (tix + (0x2000 << index)) & (0xffffc000 << index); diff --git a/sysdeps/ieee754/ldbl-128ibm/k_sinl.c b/sysdeps/ieee754/ldbl-128ibm/k_sinl.c index daa84fb..f17c0ae 100644 --- a/sysdeps/ieee754/ldbl-128ibm/k_sinl.c +++ b/sysdeps/ieee754/ldbl-128ibm/k_sinl.c @@ -119,8 +119,8 @@ __kernel_sinl(long double x, long double y, int iy) /* The following should work for double but generates the wrong index. For now the code above converts double to ieee extended to compute - the index back to double for the h value. - + the index back to double for the h value. + index = 0x3fe - (tix >> 20); hix = (tix + (0x2000 << index)) & (0xffffc000 << index); x = fabsl (x); diff --git a/sysdeps/ieee754/ldbl-128ibm/math_ldbl.h b/sysdeps/ieee754/ldbl-128ibm/math_ldbl.h index 58eb57c..046293e 100644 --- a/sysdeps/ieee754/ldbl-128ibm/math_ldbl.h +++ b/sysdeps/ieee754/ldbl-128ibm/math_ldbl.h @@ -5,7 +5,7 @@ #include <sysdeps/ieee754/ldbl-128/math_ldbl.h> #include <ieee754.h> #include <stdint.h> - + static inline void ldbl_extract_mantissa (int64_t *hi64, uint64_t *lo64, int *exp, long double x) { @@ -34,7 +34,7 @@ ldbl_extract_mantissa (int64_t *hi64, uint64_t *lo64, int *exp, long double x) lo = lo >> (ediff-53); hi |= (1ULL << 52); } - + if ((eldbl.ieee.negative != eldbl.ieee.negative2) && ((eldbl.ieee.exponent2 != 0) && (lo != 0LL))) { @@ -64,7 +64,7 @@ ldbl_insert_mantissa (int sign, int exp, int64_t hi64, u_int64_t lo64) u.ieee.exponent = exp + IBM_EXTENDED_LONG_DOUBLE_BIAS; u.ieee.exponent2 = exp-53 + IBM_EXTENDED_LONG_DOUBLE_BIAS; /* Expect 113 bits (112 bits + hidden) right justified in two longs. - The low order 53 bits (52 + hidden) go into the lower double */ + The low order 53 bits (52 + hidden) go into the lower double */ lo = (lo64 >> 7)& ((1ULL << 53) - 1); hidden2 = (lo64 >> 59) & 1ULL; /* The high order 53 bits (52 + hidden) go into the upper double */ @@ -84,7 +84,7 @@ ldbl_insert_mantissa (int sign, int exp, int64_t hi64, u_int64_t lo64) } /* The hidden bit of the lo mantissa is zero so we need to normalize the it for the low double. Shift it left until the - hidden bit is '1' then adjust the 2nd exponent accordingly. */ + hidden bit is '1' then adjust the 2nd exponent accordingly. */ if (sizeof (lo) == sizeof (long)) lzcount = __builtin_clzl (lo); @@ -122,7 +122,7 @@ ldbl_insert_mantissa (int sign, int exp, int64_t hi64, u_int64_t lo64) u.ieee.mantissa0 = (hi >> 32) & ((1ULL << 20) - 1); return u.d; } - + /* Handy utility functions to pack/unpack/cononicalize and find the nearbyint of long double implemented as double double. */ static inline long double diff --git a/sysdeps/ieee754/ldbl-128ibm/s_nextafterl.c b/sysdeps/ieee754/ldbl-128ibm/s_nextafterl.c index ff5d7d3..7e58127 100644 --- a/sysdeps/ieee754/ldbl-128ibm/s_nextafterl.c +++ b/sysdeps/ieee754/ldbl-128ibm/s_nextafterl.c @@ -56,7 +56,7 @@ long double __nextafterl(long double x, long double y) math_force_eval (u); /* raise underflow flag */ return x; } - + long double u; if(x > y) { /* x > y, x -= ulp */ if((hx==0xffefffffffffffffLL)&&(lx==0xfc8ffffffffffffeLL)) diff --git a/sysdeps/ieee754/ldbl-96/s_erfl.c b/sysdeps/ieee754/ldbl-96/s_erfl.c index b49a49b..17d2278 100644 --- a/sysdeps/ieee754/ldbl-96/s_erfl.c +++ b/sysdeps/ieee754/ldbl-96/s_erfl.c @@ -11,9 +11,9 @@ /* Long double expansions are Copyright (C) 2001 Stephen L. Moshier <moshier@na-net.ornl.gov> - and are incorporated herein by permission of the author. The author + and are incorporated herein by permission of the author. The author reserves the right to distribute this material elsewhere under different - copying permissions. These modifications are distributed here under + copying permissions. These modifications are distributed here under the following terms: This library is free software; you can redistribute it and/or diff --git a/sysdeps/ieee754/s_lib_version.c b/sysdeps/ieee754/s_lib_version.c index 7abb3e0..bb59300 100644 --- a/sysdeps/ieee754/s_lib_version.c +++ b/sysdeps/ieee754/s_lib_version.c @@ -5,7 +5,7 @@ * * Developed at SunPro, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this - * software is freely granted, provided that this notice + * software is freely granted, provided that this notice * is preserved. * ==================================================== */ diff --git a/sysdeps/mach/hurd/check_fds.c b/sysdeps/mach/hurd/check_fds.c index 9b335c2..979fcb7 100644 --- a/sysdeps/mach/hurd/check_fds.c +++ b/sysdeps/mach/hurd/check_fds.c @@ -61,7 +61,7 @@ check_one_fd (int fd, int mode) return; } } - + /* We cannot even give an error message here since it would run into the same problems. */ while (1) @@ -100,7 +100,7 @@ __libc_check_standard_fds (void) /* We don't check the standard file descriptors here. They will be checked when we initialize the file descriptor table, as part of the _hurd_fd_subinit hook. - + This function is only present to make sure that this module gets linked in when part of the static libc. */ } diff --git a/sysdeps/mach/hurd/getsockname.c b/sysdeps/mach/hurd/getsockname.c index f99bb52..4e6c517 100644 --- a/sysdeps/mach/hurd/getsockname.c +++ b/sysdeps/mach/hurd/getsockname.c @@ -47,7 +47,7 @@ __getsockname (fd, addrarg, len) if (*len > buflen) *len = buflen; - + if (buf != (char *) addr) { memcpy (addr, buf, *len); diff --git a/sysdeps/mach/hurd/net/if_ppp.h b/sysdeps/mach/hurd/net/if_ppp.h index bf5ec83..1b1c3ea 100644 --- a/sysdeps/mach/hurd/net/if_ppp.h +++ b/sysdeps/mach/hurd/net/if_ppp.h @@ -3,7 +3,7 @@ /* * if_ppp.h - Point-to-Point Protocol definitions. * - * Copyright (c) 1989 Carnegie Mellon University. + * Copyright (c) 1989 Carnegie Mellon University. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/sysdeps/mach/hurd/recvfrom.c b/sysdeps/mach/hurd/recvfrom.c index 4830adc..ea85db9 100644 --- a/sysdeps/mach/hurd/recvfrom.c +++ b/sysdeps/mach/hurd/recvfrom.c @@ -75,7 +75,7 @@ __recvfrom (fd, buf, n, flags, addrarg, addr_len) __mach_port_deallocate (__mach_task_self (), addrport); return __hurd_sockfail (fd, flags, err); } - + if (*addr_len > buflen) *addr_len = buflen; diff --git a/sysdeps/powerpc/bits/link.h b/sysdeps/powerpc/bits/link.h index b907bd6..f06092f 100644 --- a/sysdeps/powerpc/bits/link.h +++ b/sysdeps/powerpc/bits/link.h @@ -83,7 +83,7 @@ typedef struct La_ppc64_retval uint64_t lrv_r3; uint64_t lrv_r4; double lrv_fp[4]; /* f1-f4, float - complex long double. */ - uint32_t lrv_v2[4]; /* v2. */ + uint32_t lrv_v2[4]; /* v2. */ } La_ppc64_retval; diff --git a/sysdeps/powerpc/dl-procinfo.c b/sysdeps/powerpc/dl-procinfo.c index fb5051f..6f5205d 100644 --- a/sysdeps/powerpc/dl-procinfo.c +++ b/sysdeps/powerpc/dl-procinfo.c @@ -49,7 +49,7 @@ PROCINFO_CLASS const char _dl_powerpc_cap_flags[25][10] #endif #ifndef PROCINFO_DECL = { - "vsx", + "vsx", "arch_2_06", "power6x", "dfp", "pa6t", "arch_2_05", "ic_snoop", "smt", "booke", "cellbe", "power5+", "power5", "power4", diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c index 671724b..013d2bf 100644 --- a/sysdeps/powerpc/fpu/feholdexcpt.c +++ b/sysdeps/powerpc/fpu/feholdexcpt.c @@ -32,7 +32,7 @@ feholdexcept (fenv_t *envp) flag. */ new.l[1] = old.l[1] & 7; new.l[0] = old.l[0]; - + /* If the old env had any enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not generate SIGFPE. */ diff --git a/sysdeps/powerpc/fpu/fenv_const.c b/sysdeps/powerpc/fpu/fenv_const.c index d7bb79c..47761eb 100644 --- a/sysdeps/powerpc/fpu/fenv_const.c +++ b/sysdeps/powerpc/fpu/fenv_const.c @@ -16,17 +16,17 @@ License along with the GNU C Library; if not, see <http://www.gnu.org/licenses/>. */ -/* We want to specify the bit pattern of the __fe_*_env constants, so +/* We want to specify the bit pattern of the __fe_*_env constants, so pretend they're really `long long' instead of `double'. */ /* If the default argument is used we use this value. */ -const unsigned long long __fe_dfl_env __attribute__ ((aligned (8))) = +const unsigned long long __fe_dfl_env __attribute__ ((aligned (8))) = 0xfff8000000000000ULL; /* Floating-point environment where none of the exceptions are masked. */ -const unsigned long long __fe_enabled_env __attribute__ ((aligned (8))) = +const unsigned long long __fe_enabled_env __attribute__ ((aligned (8))) = 0xfff80000000000f8ULL; /* Floating-point environment with the NI bit set. */ -const unsigned long long __fe_nonieee_env __attribute__ ((aligned (8))) = +const unsigned long long __fe_nonieee_env __attribute__ ((aligned (8))) = 0xfff8000000000004ULL; diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index 953af5d..e92adb4 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -29,21 +29,21 @@ __fesetenv (const fenv_t *envp) /* get the currently set exceptions. */ new.fenv = *envp; old.fenv = fegetenv_register (); - + /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); - + /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not + FPU to run faster because it always takes the default action and can not generate SIGFPE. */ if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); - + fesetenv_register (*envp); /* Success. */ diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c index 9faf930..6500ea1 100644 --- a/sysdeps/powerpc/fpu/feupdateenv.c +++ b/sysdeps/powerpc/fpu/feupdateenv.c @@ -35,17 +35,17 @@ __feupdateenv (const fenv_t *envp) exceptions. Leave fraction rounded/inexact and FP result/CC bits unchanged. */ new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF); - + /* If the old env has no enabled exceptions and the new env has any enabled exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some hardware. */ if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) (void)__fe_nomask_env (); - + /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not + FPU to run faster because it always takes the default action and can not generate SIGFPE. */ if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) (void)__fe_mask_env (); diff --git a/sysdeps/powerpc/fpu/s_rintf.c b/sysdeps/powerpc/fpu/s_rintf.c index 7b14767..4a32a43 100644 --- a/sysdeps/powerpc/fpu/s_rintf.c +++ b/sysdeps/powerpc/fpu/s_rintf.c @@ -36,7 +36,7 @@ __rintf (float x) x = -(x - TWO23); } } - + return x; } weak_alias (__rintf, rintf) diff --git a/sysdeps/powerpc/fpu/t_sqrt.c b/sysdeps/powerpc/fpu/t_sqrt.c index c49380c..9ed7436 100644 --- a/sysdeps/powerpc/fpu/t_sqrt.c +++ b/sysdeps/powerpc/fpu/t_sqrt.c @@ -50,7 +50,7 @@ const float __t_sqrt[1024] = { 0.9847,0.5077, 0.9857,0.5072, 0.9867,0.5067, 0.9877,0.5062, 0.9887,0.5057, 0.9897,0.5052, 0.9907,0.5047, 0.9917,0.5042, 0.9926,0.5037, 0.9936,0.5032, 0.9946,0.5027, 0.9956,0.5022, 0.9966,0.5017, 0.9976,0.5012, 0.9985,0.5007, -0.9995,0.5002, +0.9995,0.5002, 1.0010,0.4995, 1.0029,0.4985, 1.0049,0.4976, 1.0068,0.4966, 1.0088,0.4957, 1.0107,0.4947, 1.0126,0.4938, 1.0145,0.4928, 1.0165,0.4919, 1.0184,0.4910, 1.0203,0.4901, 1.0222,0.4891, 1.0241,0.4882, 1.0260,0.4873, 1.0279,0.4864, diff --git a/sysdeps/powerpc/powerpc32/bits/atomic.h b/sysdeps/powerpc/powerpc32/bits/atomic.h index 3e3a1ef..a09e4d4 100644 --- a/sysdeps/powerpc/powerpc32/bits/atomic.h +++ b/sysdeps/powerpc/powerpc32/bits/atomic.h @@ -24,7 +24,7 @@ atomic operation. In that case we don't expect additional updates adjacent to the lock word after the Store Conditional and the hint should be false. */ - + #if defined _ARCH_PWR6 || defined _ARCH_PWR6X # define MUTEX_HINT_ACQ ",1" # define MUTEX_HINT_REL ",0" diff --git a/sysdeps/powerpc/powerpc32/fpu/s_floor.S b/sysdeps/powerpc/powerpc32/fpu/s_floor.S index 21154ae..168bb17 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_floor.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_floor.S @@ -59,7 +59,7 @@ ENTRY (__floor) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__floor) diff --git a/sysdeps/powerpc/powerpc32/fpu/s_floorf.S b/sysdeps/powerpc/powerpc32/fpu/s_floorf.S index e5faf2c..4d6e90c 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_floorf.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_floorf.S @@ -58,7 +58,7 @@ ENTRY (__floorf) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__floorf) diff --git a/sysdeps/powerpc/powerpc32/fpu/s_isnan.S b/sysdeps/powerpc/powerpc32/fpu/s_isnan.S index ac8b088..98d10da 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_isnan.S @@ -21,7 +21,7 @@ /* int __isnan(x) */ .machine power4 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) mffs fp0 mtfsb0 4*cr6+lt /* reset_fpscr_bit (FPSCR_VE) */ fcmpu cr7,fp1,fp1 diff --git a/sysdeps/powerpc/powerpc32/fpu/s_lround.S b/sysdeps/powerpc/powerpc32/fpu/s_lround.S index d1472ce..92dc378 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_lround.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_lround.S @@ -24,13 +24,13 @@ .LC0: /* 0.5 */ .long 0x3f000000 .section ".text" - + /* long [r3] lround (float x [fp1]) - IEEE 1003.1 lround function. IEEE specifies "round to the nearest + IEEE 1003.1 lround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "round to Nearest" mode. Instead we set "round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. It is necessary to detect when x is @@ -60,7 +60,7 @@ ENTRY (__lround) blt- cr6,.Lretzero fadd fp3,fp2,fp10 /* |x|+=0.5 bias to prepare to round. */ bge cr7,.Lconvert /* x is positive so don't negate x. */ - fnabs fp3,fp3 /* -(|x|+=0.5) */ + fnabs fp3,fp3 /* -(|x|+=0.5) */ .Lconvert: fctiwz fp4,fp3 /* Convert to Integer word lround toward 0. */ stfd fp4,8(r1) diff --git a/sysdeps/powerpc/powerpc32/fpu/s_round.S b/sysdeps/powerpc/powerpc32/fpu/s_round.S index 030204f..73a1004 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_round.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_round.S @@ -27,11 +27,11 @@ .long 0x3f000000 /* double [fp1] round (double x [fp1]) - IEEE 1003.1 round function. IEEE specifies "round to the nearest + IEEE 1003.1 round function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "Round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "Round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "Round to Nearest" mode. Instead we set "Round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. */ diff --git a/sysdeps/powerpc/powerpc32/fpu/s_roundf.S b/sysdeps/powerpc/powerpc32/fpu/s_roundf.S index adf4d35..2ed9ca7 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_roundf.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_roundf.S @@ -26,11 +26,11 @@ .long 0x3f000000 /* float [fp1] roundf (float x [fp1]) - IEEE 1003.1 round function. IEEE specifies "round to the nearest + IEEE 1003.1 round function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "Round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "Round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "Round to Nearest" mode. Instead we set "Round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. */ diff --git a/sysdeps/powerpc/powerpc32/fpu/s_trunc.S b/sysdeps/powerpc/powerpc32/fpu/s_trunc.S index fe3e2b9..0f9e360 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_trunc.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_trunc.S @@ -26,7 +26,7 @@ /* double [fp1] trunc (double x [fp1]) IEEE 1003.1 trunc function. IEEE specifies "trunc to the integer - value, in floating format, nearest to but no larger in magnitude + value, in floating format, nearest to but no larger in magnitude then the argument." We set "round toward Zero" mode and trunc by adding +-2**52 then subtracting +-2**52. */ diff --git a/sysdeps/powerpc/powerpc32/fpu/s_truncf.S b/sysdeps/powerpc/powerpc32/fpu/s_truncf.S index a74e3dc..effbede 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_truncf.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_truncf.S @@ -25,7 +25,7 @@ /* float [fp1] truncf (float x [fp1]) IEEE 1003.1 trunc function. IEEE specifies "trunc to the integer - value, in floating format, nearest to but no larger in magnitude + value, in floating format, nearest to but no larger in magnitude then the argument." We set "round toward Zero" mode and trunc by adding +-2**23 then subtracting +-2**23. */ diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S b/sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S index 2ac986d..55b2850 100644 --- a/sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S +++ b/sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S @@ -20,7 +20,7 @@ #include <math_ldbl_opt.h> /* long long int[r3, r4] __llrint (double x[fp1]) */ -ENTRY (__llrint) +ENTRY (__llrint) CALL_MCOUNT stwu r1,-16(r1) cfi_adjust_cfa_offset (16) @@ -31,7 +31,7 @@ ENTRY (__llrint) nop lwz r3,8(r1) lwz r4,12(r1) - addi r1,r1,16 + addi r1,r1,16 blr END (__llrint) diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S b/sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S index 98e3aaf..cc80fcb 100644 --- a/sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S +++ b/sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S @@ -19,7 +19,7 @@ #include <sysdep.h> /* long long int[r3, r4] __llrintf (float x[fp1]) */ -ENTRY (__llrintf) +ENTRY (__llrintf) CALL_MCOUNT stwu r1,-16(r1) cfi_adjust_cfa_offset (16) @@ -30,7 +30,7 @@ ENTRY (__llrintf) nop lwz r3,8(r1) lwz r4,12(r1) - addi r1,r1,16 + addi r1,r1,16 blr END (__llrintf) diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/s_llround.S b/sysdeps/powerpc/powerpc32/power4/fpu/s_llround.S index 07beb0a..631180f 100644 --- a/sysdeps/powerpc/powerpc32/power4/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc32/power4/fpu/s_llround.S @@ -29,11 +29,11 @@ .section ".text" /* long [r3] lround (float x [fp1]) - IEEE 1003.1 lround function. IEEE specifies "round to the nearest + IEEE 1003.1 lround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "round to Nearest" mode. Instead we set "round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S index 4f1c176..3648e4a 100644 --- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S +++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S @@ -25,20 +25,20 @@ sets the appropriate floating point exceptions. Extended checking is only needed to set errno (via __kernel_standard) if the input value is negative. - + The fsqrt will set FPCC and FU (Floating Point Unordered or NaN to indicated that the input value was negative or NaN. Use Move to Condition Register from FPSCR to copy the FPCC field to cr1. The branch on summary overflow transfers control to w_sqrt to process any error conditions. Otherwise we can return the result directly. - + This part of the function is a leaf routine, so no need to stack a frame or execute prologue/epilogue code. This means it is safe to transfer directly to w_sqrt as long as the input value (f1) is preserved. Putting the sqrt result into f2 (double parameter 2) allows passing both the input value and sqrt result into the extended wrapper so there is no need to recompute. - + This tactic avoids the overhead of stacking a frame for the normal (non-error) case. Until gcc supports prologue shrink-wrapping this is the best we can do. */ diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S index 0da5b7a..153843c 100644 --- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S +++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S @@ -25,20 +25,20 @@ sets the appropriate floating point exceptions. Extended checking is only needed to set errno (via __kernel_standard) if the input value is negative. - + The fsqrts will set FPCC and FU (Floating Point Unordered or NaN to indicated that the input value was negative or NaN. Use Move to Condition Register from FPSCR to copy the FPCC field to cr1. The branch on summary overflow transfers control to w_sqrt to process any error conditions. Otherwise we can return the result directly. - + This part of the function is a leaf routine, so no need to stack a frame or execute prologue/epilogue code. This means it is safe to transfer directly to w_sqrt as long as the input value (f1) is preserved. Putting the sqrt result into f2 (float parameter 2) allows passing both the input value and sqrt result into the extended wrapper so there is no need to recompute. - + This tactic avoids the overhead of stacking a frame for the normal (non-error) case. Until gcc supports prologue shrink-wrapping this is the best we can do. */ diff --git a/sysdeps/powerpc/powerpc32/power4/hp-timing.c b/sysdeps/powerpc/powerpc32/power4/hp-timing.c index f54a5f8..5073adb 100644 --- a/sysdeps/powerpc/powerpc32/power4/hp-timing.c +++ b/sysdeps/powerpc/powerpc32/power4/hp-timing.c @@ -1,4 +1,4 @@ -/* Support for high precision, low overhead timing functions. +/* Support for high precision, low overhead timing functions. powerpc64 version. Copyright (C) 2005-2013 Free Software Foundation, Inc. This file is part of the GNU C Library. diff --git a/sysdeps/powerpc/powerpc32/power4/memcmp.S b/sysdeps/powerpc/powerpc32/power4/memcmp.S index edec7ab..d7050a2 100644 --- a/sysdeps/powerpc/powerpc32/power4/memcmp.S +++ b/sysdeps/powerpc/powerpc32/power4/memcmp.S @@ -53,17 +53,17 @@ EALIGN (memcmp, 4, 0) blt cr1, L(bytealigned) stwu 1,-64(1) cfi_adjust_cfa_offset(64) - stw r31,48(1) + stw r31,48(1) cfi_offset(31,(48-64)) - stw r30,44(1) + stw r30,44(1) cfi_offset(30,(44-64)) bne L(unaligned) /* At this point we know both strings have the same alignment and the compare length is at least 8 bytes. rBITDIF contains the low order 2 bits of rSTR1 and cr5 contains the result of the logical compare - of rBITDIF to 0. If rBITDIF == 0 then we are already word + of rBITDIF to 0. If rBITDIF == 0 then we are already word aligned and can perform the word aligned loop. - + Otherwise we know the two strings have the same alignment (but not yet word aligned). So we force the string addresses to the next lower word boundary and special case this first word using shift left to @@ -143,7 +143,7 @@ L(Waligned): beq L(dP4) bgt cr1, L(dP3) beq cr1, L(dP2) - + /* Remainder is 4 */ .align 4 L(dP1): @@ -152,7 +152,7 @@ L(dP1): (8-15 byte compare), we want to use only volatile registers. This means we can avoid restoring non-volatile registers since we did not change any on the early exit path. The key here is the non-early - exit path only cares about the condition code (cr5), not about which + exit path only cares about the condition code (cr5), not about which register pair was used. */ lwz rWORD5, 0(rSTR1) lwz rWORD6, 0(rSTR2) @@ -170,7 +170,7 @@ L(dP1e): cmplw cr6, rWORD5, rWORD6 bne cr5, L(dLcr5) bne cr0, L(dLcr0) - + lwzu rWORD7, 16(rSTR1) lwzu rWORD8, 16(rSTR2) bne cr1, L(dLcr1) @@ -188,7 +188,7 @@ L(dP1x): bne L(d00) li rRTN, 0 blr - + /* Remainder is 8 */ .align 4 L(dP2): @@ -230,7 +230,7 @@ L(dP2x): bne L(d00) li rRTN, 0 blr - + /* Remainder is 12 */ .align 4 L(dP3): @@ -273,7 +273,7 @@ L(dP3x): bne L(d00) li rRTN, 0 blr - + /* Count is a multiple of 16, remainder is 0 */ .align 4 L(dP4): @@ -316,8 +316,8 @@ L(dLoop3): lwzu rWORD8, 16(rSTR2) bne- cr1, L(dLcr1) cmplw cr0, rWORD1, rWORD2 - bdnz+ L(dLoop) - + bdnz+ L(dLoop) + L(dL4): cmplw cr1, rWORD3, rWORD4 bne cr6, L(dLcr6) @@ -332,7 +332,7 @@ L(d24): bne cr6, L(dLcr6) L(d14): slwi. r12, rN, 3 - bne cr5, L(dLcr5) + bne cr5, L(dLcr5) L(d04): lwz r30,44(1) lwz r31,48(1) @@ -341,10 +341,10 @@ L(d04): beq L(zeroLength) /* At this point we have a remainder of 1 to 3 bytes to compare. Since we are aligned it is safe to load the whole word, and use - shift right to eliminate bits beyond the compare length. */ + shift right to eliminate bits beyond the compare length. */ L(d00): lwz rWORD1, 4(rSTR1) - lwz rWORD2, 4(rSTR2) + lwz rWORD2, 4(rSTR2) srw rWORD1, rWORD1, rN srw rWORD2, rWORD2, rN cmplw rWORD1,rWORD2 @@ -392,22 +392,22 @@ L(dLcr5x): bgtlr cr5 li rRTN, -1 blr - + .align 4 L(bytealigned): cfi_adjust_cfa_offset(-64) mtctr rN /* Power4 wants mtctr 1st in dispatch group */ /* We need to prime this loop. This loop is swing modulo scheduled - to avoid pipe delays. The dependent instruction latencies (load to + to avoid pipe delays. The dependent instruction latencies (load to compare to conditional branch) is 2 to 3 cycles. In this loop each dispatch group ends in a branch and takes 1 cycle. Effectively - the first iteration of the loop only serves to load operands and - branches based on compares are delayed until the next loop. + the first iteration of the loop only serves to load operands and + branches based on compares are delayed until the next loop. So we must precondition some registers and condition codes so that we don't exit the loop early on the first iteration. */ - + lbz rWORD1, 0(rSTR1) lbz rWORD2, 0(rSTR2) bdz- L(b11) @@ -427,7 +427,7 @@ L(bLoop): cmplw cr6, rWORD5, rWORD6 bdz- L(b3i) - + lbzu rWORD3, 1(rSTR1) lbzu rWORD4, 1(rSTR2) bne- cr1, L(bLcr1) @@ -441,10 +441,10 @@ L(bLoop): cmplw cr1, rWORD3, rWORD4 bdnz+ L(bLoop) - + /* We speculatively loading bytes before we have tested the previous bytes. But we must avoid overrunning the length (in the ctr) to - prevent these speculative loads from causing a segfault. In this + prevent these speculative loads from causing a segfault. In this case the loop will exit early (before the all pending bytes are tested. In this case we must complete the pending operations before returning. */ @@ -488,7 +488,7 @@ L(bx56): nop L(b12): bne- cr0, L(bx12) -L(bx34): +L(bx34): sub rRTN, rWORD3, rWORD4 blr @@ -497,7 +497,7 @@ L(bx12): sub rRTN, rWORD1, rWORD2 blr - .align 4 + .align 4 L(zeroLengthReturn): L(zeroLength): @@ -509,9 +509,9 @@ L(zeroLength): /* At this point we know the strings have different alignment and the compare length is at least 8 bytes. rBITDIF contains the low order 2 bits of rSTR1 and cr5 contains the result of the logical compare - of rBITDIF to 0. If rBITDIF == 0 then rStr1 is word aligned and can + of rBITDIF to 0. If rBITDIF == 0 then rStr1 is word aligned and can perform the Wunaligned loop. - + Otherwise we know that rSTR1 is not aready word aligned yet. So we can force the string addresses to the next lower word boundary and special case this first word using shift left to @@ -531,13 +531,13 @@ L(zeroLength): #define rE r0 /* Right rotation temp for rWORD6. */ #define rG r12 /* Right rotation temp for rWORD8. */ L(unaligned): - stw r29,40(r1) - cfi_offset(r29,(40-64)) + stw r29,40(r1) + cfi_offset(r29,(40-64)) clrlwi rSHL, rSTR2, 30 - stw r28,36(r1) + stw r28,36(r1) cfi_offset(r28,(36-64)) beq cr5, L(Wunaligned) - stw r27,32(r1) + stw r27,32(r1) cfi_offset(r27,(32-64)) /* Adjust the logical start of rSTR2 to compensate for the extra bits in the 1st rSTR1 W. */ @@ -545,19 +545,19 @@ L(unaligned): /* But do not attempt to address the W before that W that contains the actual start of rSTR2. */ clrrwi rSTR2, rSTR2, 2 - stw r26,28(r1) + stw r26,28(r1) cfi_offset(r26,(28-64)) /* Compute the left/right shift counts for the unalign rSTR2, - compensating for the logical (W aligned) start of rSTR1. */ + compensating for the logical (W aligned) start of rSTR1. */ clrlwi rSHL, r27, 30 - clrrwi rSTR1, rSTR1, 2 - stw r25,24(r1) + clrrwi rSTR1, rSTR1, 2 + stw r25,24(r1) cfi_offset(r25,(24-64)) slwi rSHL, rSHL, 3 cmplw cr5, r27, rSTR2 add rN, rN, rBITDIF slwi r11, rBITDIF, 3 - stw r24,20(r1) + stw r24,20(r1) cfi_offset(r24,(20-64)) subfic rSHR, rSHL, 32 srwi rTMP, rN, 4 /* Divide by 16 */ @@ -633,16 +633,16 @@ L(duPs4): compare length is at least 8 bytes. */ .align 4 L(Wunaligned): - stw r27,32(r1) + stw r27,32(r1) cfi_offset(r27,(32-64)) clrrwi rSTR2, rSTR2, 2 - stw r26,28(r1) + stw r26,28(r1) cfi_offset(r26,(28-64)) srwi rTMP, rN, 4 /* Divide by 16 */ - stw r25,24(r1) + stw r25,24(r1) cfi_offset(r25,(24-64)) andi. rBITDIF, rN, 12 /* Get the W remainder */ - stw r24,20(r1) + stw r24,20(r1) cfi_offset(r24,(20-64)) slwi rSHL, rSHL, 3 lwz rWORD6, 0(rSTR2) @@ -656,7 +656,7 @@ L(Wunaligned): mtctr rTMP /* Power4 wants mtctr 1st in dispatch group */ bgt cr1, L(duP3) beq cr1, L(duP2) - + /* Remainder is 4 */ .align 4 L(duP1): @@ -687,7 +687,7 @@ L(duP1e): bne cr0, L(duLcr0) or rWORD6, rE, rF cmplw cr6, rWORD5, rWORD6 - b L(duLoop3) + b L(duLoop3) .align 4 /* At this point we exit early with the first word compare complete and remainder of 0 to 3 bytes. See L(du14) for details on @@ -751,7 +751,7 @@ L(duP2x): lwz rWORD2, 4(rSTR2) srw rA, rWORD2, rSHR b L(dutrim) - + /* Remainder is 12 */ .align 4 L(duP3): @@ -801,7 +801,7 @@ L(duP3x): lwz rWORD2, 4(rSTR2) srw rA, rWORD2, rSHR b L(dutrim) - + /* Count is a multiple of 16, remainder is 0 */ .align 4 L(duP4): @@ -867,8 +867,8 @@ L(duLoop3): srw rG, rWORD8, rSHR slw rB, rWORD8, rSHL or rWORD8, rG, rH - bdnz+ L(duLoop) - + bdnz+ L(duLoop) + L(duL4): bne cr1, L(duLcr1) cmplw cr1, rWORD3, rWORD4 @@ -886,9 +886,9 @@ L(du14): slwi. rN, rN, 3 bne cr5, L(duLcr5) /* At this point we have a remainder of 1 to 3 bytes to compare. We use - shift right to eliminate bits beyond the compare length. + shift right to eliminate bits beyond the compare length. - However it may not be safe to load rWORD2 which may be beyond the + However it may not be safe to load rWORD2 which may be beyond the string length. So we compare the bit length of the remainder to the right shift count (rSHR). If the bit count is less than or equal we do not need to load rWORD2 (all significant bits are already in @@ -903,13 +903,13 @@ L(du14): L(dutrim): lwz rWORD1, 4(rSTR1) lwz r31,48(1) - subfic rN, rN, 32 /* Shift count is 32 - (rN * 8). */ + subfic rN, rN, 32 /* Shift count is 32 - (rN * 8). */ or rWORD2, rA, rB lwz r30,44(1) lwz r29,40(r1) srw rWORD1, rWORD1, rN srw rWORD2, rWORD2, rN - lwz r28,36(r1) + lwz r28,36(r1) lwz r27,32(r1) cmplw rWORD1,rWORD2 li rRTN,0 @@ -923,9 +923,9 @@ L(duLcr0): lwz r31,48(1) lwz r30,44(1) li rRTN, 1 - bgt cr0, L(dureturn29) + bgt cr0, L(dureturn29) lwz r29,40(r1) - lwz r28,36(r1) + lwz r28,36(r1) li rRTN, -1 b L(dureturn27) .align 4 @@ -933,9 +933,9 @@ L(duLcr1): lwz r31,48(1) lwz r30,44(1) li rRTN, 1 - bgt cr1, L(dureturn29) + bgt cr1, L(dureturn29) lwz r29,40(r1) - lwz r28,36(r1) + lwz r28,36(r1) li rRTN, -1 b L(dureturn27) .align 4 @@ -943,9 +943,9 @@ L(duLcr6): lwz r31,48(1) lwz r30,44(1) li rRTN, 1 - bgt cr6, L(dureturn29) + bgt cr6, L(dureturn29) lwz r29,40(r1) - lwz r28,36(r1) + lwz r28,36(r1) li rRTN, -1 b L(dureturn27) .align 4 @@ -953,9 +953,9 @@ L(duLcr5): lwz r31,48(1) lwz r30,44(1) li rRTN, 1 - bgt cr5, L(dureturn29) + bgt cr5, L(dureturn29) lwz r29,40(r1) - lwz r28,36(r1) + lwz r28,36(r1) li rRTN, -1 b L(dureturn27) .align 3 @@ -965,14 +965,14 @@ L(duZeroReturn): L(dureturn): lwz r31,48(1) lwz r30,44(1) -L(dureturn29): +L(dureturn29): lwz r29,40(r1) - lwz r28,36(r1) -L(dureturn27): + lwz r28,36(r1) +L(dureturn27): lwz r27,32(r1) -L(dureturn26): +L(dureturn26): lwz r26,28(r1) -L(dureturn25): +L(dureturn25): lwz r25,24(r1) lwz r24,20(r1) lwz 1,0(1) diff --git a/sysdeps/powerpc/powerpc32/power4/memset.S b/sysdeps/powerpc/powerpc32/power4/memset.S index 1e8785c..c2d288b 100644 --- a/sysdeps/powerpc/powerpc32/power4/memset.S +++ b/sysdeps/powerpc/powerpc32/power4/memset.S @@ -162,7 +162,7 @@ L(cacheAligned): add rMEMP,rMEMP,rCLS b L(cacheAligned) -/* We are here because the cache line size was set and the remainder +/* We are here because the cache line size was set and the remainder (rLEN) is less than the actual cache line size. So set up the preconditions for L(nondcbz) and go there. */ L(handletail32): diff --git a/sysdeps/powerpc/powerpc32/power4/wordcopy.c b/sysdeps/powerpc/powerpc32/power4/wordcopy.c index 6dd0fa3..5d857f6 100644 --- a/sysdeps/powerpc/powerpc32/power4/wordcopy.c +++ b/sysdeps/powerpc/powerpc32/power4/wordcopy.c @@ -37,7 +37,7 @@ _wordcopy_fwd_aligned (dstp, srcp, len) if (len & 1) { ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; srcp += OPSIZ; @@ -88,10 +88,10 @@ _wordcopy_fwd_dest_aligned (dstp, srcp, len) { a1 = ((op_t *) srcp)[1]; ((op_t *) dstp)[0] = MERGE (a0, sh_1, a1, sh_2); - + if (len == 1) return; - + a0 = a1; srcp += OPSIZ; dstp += OPSIZ; @@ -131,7 +131,7 @@ _wordcopy_bwd_aligned (dstp, srcp, len) srcp -= OPSIZ; dstp -= OPSIZ; ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; len -= 1; diff --git a/sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S b/sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S index 558bd2a..ecd37c3 100644 --- a/sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S @@ -18,13 +18,13 @@ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long [r3] llround (float x [fp1]) - IEEE 1003.1 lround function. IEEE specifies "round to the nearest + IEEE 1003.1 lround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use the Floating Convert to Integer Word with round to zero instruction. */ diff --git a/sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S b/sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S index 0fa359d..d4da625 100644 --- a/sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S +++ b/sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S @@ -17,13 +17,13 @@ <http://www.gnu.org/licenses/>. */ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long [r3] lround (float x [fp1]) - IEEE 1003.1 lround function. IEEE specifies "round to the nearest + IEEE 1003.1 lround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use the Floating Convert to Integer Word with round to zero instruction. */ diff --git a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S index 23559aa..ed11d5a 100644 --- a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S +++ b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S @@ -25,19 +25,19 @@ sets the appropriate floating point exceptions. Extended checking is only needed to set errno (via __kernel_standard) if the input value is negative. - + So compare the input value against the absolute value of itself. This will compare equal unless the value is negative (EDOM) or a NAN, in which case we branch to the extend wrapper. If equal we can return the result directly. - + This part of the function looks like a leaf routine, so no need to stack a frame or execute prologue/epilogue code. It is safe to branch directly to w_sqrt as long as the input value (f1) is preserved. Putting the sqrt result into f2 (float parameter 2) allows passing both the input value and sqrt result into the extended wrapper so there is no need to recompute. - + This tactic avoids the overhead of stacking a frame for the normal (non-error) case. Until gcc supports prologue shrink-wrapping this is the best we can do. */ diff --git a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S index 590c24c..2049172 100644 --- a/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S +++ b/sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S @@ -25,19 +25,19 @@ sets the appropriate floating point exceptions. Extended checking is only needed to set errno (via __kernel_standard) if the input value is negative. - + So compare the input value against the absolute value of itself. This will compare equal unless the value is negative (EDOM) or a NAN, in which case we branch to the extend wrapper. If equal we can return the result directly. - + This part of the function looks like a leaf routine, so no need to stack a frame or execute prologue/epilogue code. It is safe to branch directly to w_sqrt as long as the input value (f1) is preserved. Putting the sqrt result into f2 (float parameter 2) allows passing both the input value and sqrt result into the extended wrapper so there is no need to recompute. - + This tactic avoids the overhead of stacking a frame for the normal (non-error) case. Until gcc supports prologue shrink-wrapping this is the best we can do. */ diff --git a/sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S b/sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S index 86f51bb..3344b31 100644 --- a/sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S +++ b/sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S @@ -20,7 +20,7 @@ #include <math_ldbl_opt.h> /* long long int[r3, r4] __llrint (double x[fp1]) */ -ENTRY (__llrint) +ENTRY (__llrint) CALL_MCOUNT stwu r1,-16(r1) cfi_adjust_cfa_offset (16) @@ -31,7 +31,7 @@ ENTRY (__llrint) ori r1,r1,0 lwz r3,8(r1) lwz r4,12(r1) - addi r1,r1,16 + addi r1,r1,16 blr END (__llrint) diff --git a/sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S b/sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S index 1b06e2b..7f64f8d 100644 --- a/sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S +++ b/sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S @@ -19,7 +19,7 @@ #include <sysdep.h> /* long long int[r3, r4] __llrintf (float x[fp1]) */ -ENTRY (__llrintf) +ENTRY (__llrintf) CALL_MCOUNT stwu r1,-16(r1) cfi_adjust_cfa_offset (16) @@ -30,7 +30,7 @@ ENTRY (__llrintf) ori r1,r1,0 lwz r3,8(r1) lwz r4,12(r1) - addi r1,r1,16 + addi r1,r1,16 blr END (__llrintf) diff --git a/sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S b/sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S index bfc5efb..0ff04cb 100644 --- a/sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S @@ -18,13 +18,13 @@ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long [r3] llround (float x [fp1]) - IEEE 1003.1 lround function. IEEE specifies "round to the nearest + IEEE 1003.1 lround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use the Floating Convert to Integer Word with round to zero instruction. */ diff --git a/sysdeps/powerpc/powerpc32/power6/memcpy.S b/sysdeps/powerpc/powerpc32/power6/memcpy.S index d900028..c3d55b7 100644 --- a/sysdeps/powerpc/powerpc32/power6/memcpy.S +++ b/sysdeps/powerpc/powerpc32/power6/memcpy.S @@ -21,7 +21,7 @@ /* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]); Returns 'dst'. - Memcpy handles short copies (< 32-bytes) using a binary move blocks + Memcpy handles short copies (< 32-bytes) using a binary move blocks (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled with the appropriate combination of byte and halfword load/stores. There is minimal effort to optimize the alignment of short moves. diff --git a/sysdeps/powerpc/powerpc32/power6/wordcopy.c b/sysdeps/powerpc/powerpc32/power6/wordcopy.c index bcb6176..4106e5c 100644 --- a/sysdeps/powerpc/powerpc32/power6/wordcopy.c +++ b/sysdeps/powerpc/powerpc32/power6/wordcopy.c @@ -38,7 +38,7 @@ _wordcopy_fwd_aligned (dstp, srcp, len) if (len & 1) { ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; srcp += OPSIZ; @@ -105,10 +105,10 @@ _wordcopy_fwd_dest_aligned (dstp, srcp, len) { a1 = ((op_t *) srcp)[1]; ((op_t *) dstp)[0] = MERGE (a0, sh_1, a1, sh_2); - + if (len == 1) return; - + a0 = a1; srcp += OPSIZ; dstp += OPSIZ; @@ -137,7 +137,7 @@ _wordcopy_bwd_aligned (dstp, srcp, len) srcp -= OPSIZ; dstp -= OPSIZ; ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; len -= 1; diff --git a/sysdeps/powerpc/powerpc32/power6x/fpu/s_lround.S b/sysdeps/powerpc/powerpc32/power6x/fpu/s_lround.S index 950b695..0a04051 100644 --- a/sysdeps/powerpc/powerpc32/power6x/fpu/s_lround.S +++ b/sysdeps/powerpc/powerpc32/power6x/fpu/s_lround.S @@ -18,13 +18,13 @@ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long [r3] lround (float x [fp1]) - IEEE 1003.1 lround function. IEEE specifies "round to the nearest + IEEE 1003.1 lround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use the Floating Convert to Integer Word with round to zero instruction. */ diff --git a/sysdeps/powerpc/powerpc64/fpu/s_ceill.S b/sysdeps/powerpc/powerpc64/fpu/s_ceill.S index bffac39..3ef7b9f 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_ceill.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_ceill.S @@ -69,7 +69,7 @@ ENTRY (__ceill) mtfsf 0x01,fp11 /* restore previous rounding mode. */ fnabs fp1,fp1 /* if (x == 0.0) */ blr /* x = -0.0; */ - + /* The high double is > TWO52 so we need to round the low double and perhaps the high double. In this case we have to round the low double and handle any adjustment to the high double that may be @@ -93,7 +93,7 @@ ENTRY (__ceill) beqlr- cr0 mtfsfi 7,2 /* Set rounding mode toward +inf. */ fdiv fp8,fp1,fp13 /* x_high/TWO52 */ - + bng- cr6,.L6 /* if (x > 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ @@ -110,7 +110,7 @@ ENTRY (__ceill) b .L9 .L6: /* if (x < 0.0) */ fctidz fp0,fp8 - fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ + fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ bnl cr5,.L7 /* if (x_low < 0.0) */ fmr fp3,fp1 fmr fp4,fp2 diff --git a/sysdeps/powerpc/powerpc64/fpu/s_floor.S b/sysdeps/powerpc/powerpc64/fpu/s_floor.S index a8e79e9..44bd832 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_floor.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_floor.S @@ -48,7 +48,7 @@ EALIGN (__floor, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__floor) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_floorf.S b/sysdeps/powerpc/powerpc64/fpu/s_floorf.S index f65e3b8..a0a22e7 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_floorf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_floorf.S @@ -47,7 +47,7 @@ EALIGN (__floorf, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__floorf) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/fpu/s_isnan.S index 3fd62ae..95eb81e 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_isnan.S @@ -21,7 +21,7 @@ /* int __isnan(x) */ .machine power4 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 mffs fp0 mtfsb0 4*cr6+lt /* reset_fpscr_bit (FPSCR_VE) */ diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llrint.S b/sysdeps/powerpc/powerpc64/fpu/s_llrint.S index 82b8df4..7019347 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llrint.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llrint.S @@ -20,14 +20,14 @@ #include <math_ldbl_opt.h> /* long long int[r3] __llrint (double x[fp1]) */ -ENTRY (__llrint) +ENTRY (__llrint) CALL_MCOUNT 0 fctid fp13,fp1 stfd fp13,-16(r1) nop /* Insure the following load is in a different dispatch group */ nop /* to avoid pipe stall on POWER4&5. */ nop - ld r3,-16(r1) + ld r3,-16(r1) blr END (__llrint) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S b/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S index 3de36c2..4673967 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llrintf.S @@ -19,14 +19,14 @@ #include <sysdep.h> /* long long int[r3] __llrintf (float x[fp1]) */ -ENTRY (__llrintf) +ENTRY (__llrintf) CALL_MCOUNT 0 fctid fp13,fp1 stfd fp13,-16(r1) nop /* Insure the following load is in a different dispatch group */ nop /* to avoid pipe stall on POWER4&5. */ nop - ld r3,-16(r1) + ld r3,-16(r1) blr END (__llrintf) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llround.S b/sysdeps/powerpc/powerpc64/fpu/s_llround.S index 286aae3..54b8341 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llround.S @@ -25,13 +25,13 @@ .LC1: /* 0.5 */ .tc FD_3fe00000_0[TC],0x3fe0000000000000 .section ".text" - + /* long long [r3] llround (double x [fp1]) - IEEE 1003.1 llround function. IEEE specifies "round to the nearest + IEEE 1003.1 llround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "round to Nearest" mode. Instead we set "round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. diff --git a/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S b/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S index b1083a8..25c61f2 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_llroundf.S @@ -24,13 +24,13 @@ .LC1: /* 0.5 */ .tc FD_3fe00000_0[TC],0x3fe0000000000000 .section ".text" - + /* long long [r3] llroundf (float x [fp1]) - IEEE 1003.1 llroundf function. IEEE specifies "roundf to the nearest + IEEE 1003.1 llroundf function. IEEE specifies "roundf to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "roundf to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "roundf to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "round to Nearest" mode. Instead we set "round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. diff --git a/sysdeps/powerpc/powerpc64/fpu/s_round.S b/sysdeps/powerpc/powerpc64/fpu/s_round.S index 022be84..3c7437a 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_round.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_round.S @@ -25,13 +25,13 @@ .LC1: /* 0.5 */ .tc FD_3fe00000_0[TC],0x3fe0000000000000 .section ".text" - + /* double [fp1] round (double x [fp1]) - IEEE 1003.1 round function. IEEE specifies "round to the nearest + IEEE 1003.1 round function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "Round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "Round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "Round to Nearest" mode. Instead we set "Round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. */ @@ -63,7 +63,7 @@ EALIGN (__round, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__round) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_roundf.S b/sysdeps/powerpc/powerpc64/fpu/s_roundf.S index dc50d1a..980a77b 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_roundf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_roundf.S @@ -24,13 +24,13 @@ .LC1: /* 0.5 */ .tc FD_3f000000_0[TC],0x3f00000000000000 .section ".text" - + /* float [fp1] roundf (float x [fp1]) - IEEE 1003.1 round function. IEEE specifies "round to the nearest + IEEE 1003.1 round function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "Round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "Round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we can't use the PowerPC "Round to Nearest" mode. Instead we set "Round toward Zero" mode and round by adding +-0.5 before rounding to the integer value. */ @@ -62,7 +62,7 @@ EALIGN (__roundf, 4, 0) fnabs fp1,fp1 /* if (x == 0.0) */ /* x = -0.0; */ .L9: - mtfsf 0x01,fp11 /* restore previous rounding mode. */ + mtfsf 0x01,fp11 /* restore previous rounding mode. */ blr END (__roundf) diff --git a/sysdeps/powerpc/powerpc64/fpu/s_roundl.S b/sysdeps/powerpc/powerpc64/fpu/s_roundl.S index 5cc41c0..547b721 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_roundl.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_roundl.S @@ -91,7 +91,7 @@ ENTRY (__roundl) beqlr- cr0 mtfsfi 7,1 /* Set rounding mode toward 0. */ fdiv fp8,fp1,fp13 /* x_high/TWO52 */ - + bng- cr6,.L6 /* if (x > 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ @@ -109,7 +109,7 @@ ENTRY (__roundl) b .L9 .L6: /* if (x < 0.0) */ fctidz fp0,fp8 - fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ + fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ bnl cr5,.L7 /* if (x_low < 0.0) */ fmr fp3,fp1 fmr fp4,fp2 diff --git a/sysdeps/powerpc/powerpc64/fpu/s_trunc.S b/sysdeps/powerpc/powerpc64/fpu/s_trunc.S index 5b018fb..f123873 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_trunc.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_trunc.S @@ -23,10 +23,10 @@ .LC0: /* 2**52 */ .tc FD_43300000_0[TC],0x4330000000000000 .section ".text" - + /* double [fp1] trunc (double x [fp1]) IEEE 1003.1 trunc function. IEEE specifies "trunc to the integer - value, in floating format, nearest to but no larger in magnitude + value, in floating format, nearest to but no larger in magnitude then the argument." We set "round toward Zero" mode and trunc by adding +-2**52 then subtracting +-2**52. */ diff --git a/sysdeps/powerpc/powerpc64/fpu/s_truncf.S b/sysdeps/powerpc/powerpc64/fpu/s_truncf.S index 9f35240..5ea5f3d 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_truncf.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_truncf.S @@ -22,10 +22,10 @@ .LC0: /* 2**23 */ .tc FD_4b000000_0[TC],0x4b00000000000000 .section ".text" - + /* float [fp1] truncf (float x [fp1]) IEEE 1003.1 trunc function. IEEE specifies "trunc to the integer - value, in floating format, nearest to but no larger in magnitude + value, in floating format, nearest to but no larger in magnitude then the argument." We set "round toward Zero" mode and trunc by adding +-2**23 then subtracting +-2**23. */ diff --git a/sysdeps/powerpc/powerpc64/fpu/s_truncl.S b/sysdeps/powerpc/powerpc64/fpu/s_truncl.S index 03f4527..06fd7db 100644 --- a/sysdeps/powerpc/powerpc64/fpu/s_truncl.S +++ b/sysdeps/powerpc/powerpc64/fpu/s_truncl.S @@ -79,7 +79,7 @@ ENTRY (__truncl) beqlr- cr0 mtfsfi 7,1 /* Set rounding mode toward 0. */ fdiv fp8,fp1,fp13 /* x_high/TWO52 */ - + bng- cr6,.L6 /* if (x > 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ @@ -98,7 +98,7 @@ ENTRY (__truncl) .L6: /* if (x < 0.0) */ fctidz fp0,fp8 fcfid fp8,fp0 /* tau = floor(x_high/TWO52); */ - fadd fp8,fp8,fp8 /* tau++; Make tau even */ + fadd fp8,fp8,fp8 /* tau++; Make tau even */ bnl cr5,.L7 /* if (x_low < 0.0) */ fmr fp3,fp1 fmr fp4,fp2 diff --git a/sysdeps/powerpc/powerpc64/hp-timing.c b/sysdeps/powerpc/powerpc64/hp-timing.c index f54a5f8..5073adb 100644 --- a/sysdeps/powerpc/powerpc64/hp-timing.c +++ b/sysdeps/powerpc/powerpc64/hp-timing.c @@ -1,4 +1,4 @@ -/* Support for high precision, low overhead timing functions. +/* Support for high precision, low overhead timing functions. powerpc64 version. Copyright (C) 2005-2013 Free Software Foundation, Inc. This file is part of the GNU C Library. diff --git a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c index bd0f9f0..78bba57 100644 --- a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c +++ b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrt.c @@ -35,10 +35,10 @@ __sqrt (double x) /* wrapper sqrt */ #else if (__builtin_expect (_LIB_VERSION == _IEEE_, 0)) return z; - + if (__builtin_expect (x != x, 0)) return z; - + if (__builtin_expect (x < 0.0, 0)) return __kernel_standard (x, x, 26); /* sqrt(negative) */ else diff --git a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c index 07c4dc1..12d9f62 100644 --- a/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c +++ b/sysdeps/powerpc/powerpc64/power4/fpu/w_sqrtf.c @@ -38,10 +38,10 @@ __sqrtf (float x) /* wrapper sqrtf */ if (__builtin_expect (_LIB_VERSION == _IEEE_, 0)) return z; - + if (__builtin_expect (x != x, 0)) return z; - + if (__builtin_expect (x < 0.0, 0)) /* sqrtf(negative) */ return (float) __kernel_standard ((double) x, (double) x, 126); diff --git a/sysdeps/powerpc/powerpc64/power4/memcmp.S b/sysdeps/powerpc/powerpc64/power4/memcmp.S index 6378ecb..69caedc 100644 --- a/sysdeps/powerpc/powerpc64/power4/memcmp.S +++ b/sysdeps/powerpc/powerpc64/power4/memcmp.S @@ -51,17 +51,17 @@ EALIGN (memcmp, 4, 0) /* If less than 8 bytes or not aligned, use the unaligned byte loop. */ blt cr1, L(bytealigned) - std rWORD8,-8(r1) + std rWORD8,-8(r1) cfi_offset(rWORD8,-8) - std rWORD7,-16(r1) + std rWORD7,-16(r1) cfi_offset(rWORD7,-16) bne L(unaligned) /* At this point we know both strings have the same alignment and the compare length is at least 8 bytes. rBITDIF contains the low order 3 bits of rSTR1 and cr5 contains the result of the logical compare - of rBITDIF to 0. If rBITDIF == 0 then we are already double word + of rBITDIF to 0. If rBITDIF == 0 then we are already double word aligned and can perform the DWaligned loop. - + Otherwise we know the two strings have the same alignment (but not yet DW). So we can force the string addresses to the next lower DW boundary and special case this first DW word using shift left to @@ -141,7 +141,7 @@ L(DWaligned): beq L(dP4) bgt cr1, L(dP3) beq cr1, L(dP2) - + /* Remainder is 8 */ .align 4 L(dP1): @@ -150,7 +150,7 @@ L(dP1): (8-15 byte compare), we want to use only volatile registers. This means we can avoid restoring non-volatile registers since we did not change any on the early exit path. The key here is the non-early - exit path only cares about the condition code (cr5), not about which + exit path only cares about the condition code (cr5), not about which register pair was used. */ ld rWORD5, 0(rSTR1) ld rWORD6, 0(rSTR2) @@ -168,7 +168,7 @@ L(dP1e): cmpld cr6, rWORD5, rWORD6 bne cr5, L(dLcr5) bne cr0, L(dLcr0) - + ldu rWORD7, 32(rSTR1) ldu rWORD8, 32(rSTR2) bne cr1, L(dLcr1) @@ -185,7 +185,7 @@ L(dP1x): bne L(d00) li rRTN, 0 blr - + /* Remainder is 16 */ .align 4 L(dP2): @@ -226,7 +226,7 @@ L(dP2x): bne L(d00) li rRTN, 0 blr - + /* Remainder is 24 */ .align 4 L(dP3): @@ -268,7 +268,7 @@ L(dP3x): bne L(d00) li rRTN, 0 blr - + /* Count is a multiple of 32, remainder is 0 */ .align 4 L(dP4): @@ -311,8 +311,8 @@ L(dLoop3): ldu rWORD8, 32(rSTR2) bne- cr1, L(dLcr1) cmpld cr0, rWORD1, rWORD2 - bdnz+ L(dLoop) - + bdnz+ L(dLoop) + L(dL4): cmpld cr1, rWORD3, rWORD4 bne cr6, L(dLcr6) @@ -327,7 +327,7 @@ L(d24): bne cr6, L(dLcr6) L(d14): sldi. r12, rN, 3 - bne cr5, L(dLcr5) + bne cr5, L(dLcr5) L(d04): ld rWORD8,-8(r1) ld rWORD7,-16(r1) @@ -338,7 +338,7 @@ L(d04): shift right double to eliminate bits beyond the compare length. */ L(d00): ld rWORD1, 8(rSTR1) - ld rWORD2, 8(rSTR2) + ld rWORD2, 8(rSTR2) srd rWORD1, rWORD1, rN srd rWORD2, rWORD2, rN cmpld cr5, rWORD1, rWORD2 @@ -378,22 +378,22 @@ L(dLcr5x): bgtlr cr5 li rRTN, -1 blr - + .align 4 L(bytealigned): mtctr rN /* Power4 wants mtctr 1st in dispatch group */ beq- cr6, L(zeroLength) /* We need to prime this loop. This loop is swing modulo scheduled - to avoid pipe delays. The dependent instruction latencies (load to + to avoid pipe delays. The dependent instruction latencies (load to compare to conditional branch) is 2 to 3 cycles. In this loop each dispatch group ends in a branch and takes 1 cycle. Effectively - the first iteration of the loop only serves to load operands and - branches based on compares are delayed until the next loop. + the first iteration of the loop only serves to load operands and + branches based on compares are delayed until the next loop. So we must precondition some registers and condition codes so that we don't exit the loop early on the first iteration. */ - + lbz rWORD1, 0(rSTR1) lbz rWORD2, 0(rSTR2) bdz- L(b11) @@ -413,7 +413,7 @@ L(bLoop): cmpld cr6, rWORD5, rWORD6 bdz- L(b3i) - + lbzu rWORD3, 1(rSTR1) lbzu rWORD4, 1(rSTR2) bne- cr1, L(bLcr1) @@ -427,10 +427,10 @@ L(bLoop): cmpld cr1, rWORD3, rWORD4 bdnz+ L(bLoop) - + /* We speculatively loading bytes before we have tested the previous bytes. But we must avoid overrunning the length (in the ctr) to - prevent these speculative loads from causing a segfault. In this + prevent these speculative loads from causing a segfault. In this case the loop will exit early (before the all pending bytes are tested. In this case we must complete the pending operations before returning. */ @@ -474,14 +474,14 @@ L(bx56): nop L(b12): bne- cr0, L(bx12) -L(bx34): +L(bx34): sub rRTN, rWORD3, rWORD4 blr L(b11): L(bx12): sub rRTN, rWORD1, rWORD2 blr - .align 4 + .align 4 L(zeroLengthReturn): ld rWORD8,-8(r1) ld rWORD7,-16(r1) @@ -493,9 +493,9 @@ L(zeroLength): /* At this point we know the strings have different alignment and the compare length is at least 8 bytes. rBITDIF contains the low order 3 bits of rSTR1 and cr5 contains the result of the logical compare - of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word + of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word aligned and can perform the DWunaligned loop. - + Otherwise we know that rSTR1 is not already DW aligned yet. So we can force the string addresses to the next lower DW boundary and special case this first DW word using shift left to @@ -515,14 +515,14 @@ L(zeroLength): #define rE r0 /* Right rotation temp for rWORD6. */ #define rG r12 /* Right rotation temp for rWORD8. */ L(unaligned): - std r29,-24(r1) + std r29,-24(r1) cfi_offset(r29,-24) clrldi rSHL, rSTR2, 61 beq- cr6, L(duzeroLength) - std r28,-32(r1) + std r28,-32(r1) cfi_offset(r28,-32) beq cr5, L(DWunaligned) - std r27,-40(r1) + std r27,-40(r1) cfi_offset(r27,-40) /* Adjust the logical start of rSTR2 ro compensate for the extra bits in the 1st rSTR1 DW. */ @@ -530,19 +530,19 @@ L(unaligned): /* But do not attempt to address the DW before that DW that contains the actual start of rSTR2. */ clrrdi rSTR2, rSTR2, 3 - std r26,-48(r1) + std r26,-48(r1) cfi_offset(r26,-48) /* Compute the left/right shift counts for the unalign rSTR2, - compensating for the logical (DW aligned) start of rSTR1. */ + compensating for the logical (DW aligned) start of rSTR1. */ clrldi rSHL, r27, 61 - clrrdi rSTR1, rSTR1, 3 - std r25,-56(r1) + clrrdi rSTR1, rSTR1, 3 + std r25,-56(r1) cfi_offset(r25,-56) sldi rSHL, rSHL, 3 cmpld cr5, r27, rSTR2 add rN, rN, rBITDIF sldi r11, rBITDIF, 3 - std r24,-64(r1) + std r24,-64(r1) cfi_offset(r24,-64) subfic rSHR, rSHL, 64 srdi rTMP, rN, 5 /* Divide by 32 */ @@ -618,16 +618,16 @@ L(duPs4): compare length is at least 8 bytes. */ .align 4 L(DWunaligned): - std r27,-40(r1) + std r27,-40(r1) cfi_offset(r27,-40) clrrdi rSTR2, rSTR2, 3 - std r26,-48(r1) + std r26,-48(r1) cfi_offset(r26,-48) srdi rTMP, rN, 5 /* Divide by 32 */ - std r25,-56(r1) + std r25,-56(r1) cfi_offset(r25,-56) andi. rBITDIF, rN, 24 /* Get the DW remainder */ - std r24,-64(r1) + std r24,-64(r1) cfi_offset(r24,-64) sldi rSHL, rSHL, 3 ld rWORD6, 0(rSTR2) @@ -641,7 +641,7 @@ L(DWunaligned): mtctr rTMP /* Power4 wants mtctr 1st in dispatch group */ bgt cr1, L(duP3) beq cr1, L(duP2) - + /* Remainder is 8 */ .align 4 L(duP1): @@ -672,7 +672,7 @@ L(duP1e): bne cr0, L(duLcr0) or rWORD6, rE, rF cmpld cr6, rWORD5, rWORD6 - b L(duLoop3) + b L(duLoop3) .align 4 /* At this point we exit early with the first double word compare complete and remainder of 0 to 7 bytes. See L(du14) for details on @@ -736,7 +736,7 @@ L(duP2x): ld rWORD2, 8(rSTR2) srd rA, rWORD2, rSHR b L(dutrim) - + /* Remainder is 24 */ .align 4 L(duP3): @@ -786,7 +786,7 @@ L(duP3x): ld rWORD2, 8(rSTR2) srd rA, rWORD2, rSHR b L(dutrim) - + /* Count is a multiple of 32, remainder is 0 */ .align 4 L(duP4): @@ -852,8 +852,8 @@ L(duLoop3): srd rG, rWORD8, rSHR sld rB, rWORD8, rSHL or rWORD8, rG, rH - bdnz+ L(duLoop) - + bdnz+ L(duLoop) + L(duL4): bne cr1, L(duLcr1) cmpld cr1, rWORD3, rWORD4 @@ -875,7 +875,7 @@ L(du14): This allows the use of double word subtract to compute the final result. - However it may not be safe to load rWORD2 which may be beyond the + However it may not be safe to load rWORD2 which may be beyond the string length. So we compare the bit length of the remainder to the right shift count (rSHR). If the bit count is less than or equal we do not need to load rWORD2 (all significant bits are already in @@ -890,16 +890,16 @@ L(du14): L(dutrim): ld rWORD1, 8(rSTR1) ld rWORD8,-8(r1) - subfic rN, rN, 64 /* Shift count is 64 - (rN * 8). */ + subfic rN, rN, 64 /* Shift count is 64 - (rN * 8). */ or rWORD2, rA, rB - ld rWORD7,-16(r1) + ld rWORD7,-16(r1) ld r29,-24(r1) srd rWORD1, rWORD1, rN srd rWORD2, rWORD2, rN - ld r28,-32(r1) + ld r28,-32(r1) ld r27,-40(r1) li rRTN, 0 - cmpld cr0, rWORD1, rWORD2 + cmpld cr0, rWORD1, rWORD2 ld r26,-48(r1) ld r25,-56(r1) beq cr0, L(dureturn24) @@ -913,7 +913,7 @@ L(duLcr0): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr0, L(dureturn29) + bgt cr0, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -923,7 +923,7 @@ L(duLcr1): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr1, L(dureturn29) + bgt cr1, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -933,7 +933,7 @@ L(duLcr6): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr6, L(dureturn29) + bgt cr6, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -943,7 +943,7 @@ L(duLcr5): ld rWORD8,-8(r1) ld rWORD7,-16(r1) li rRTN, 1 - bgt cr5, L(dureturn29) + bgt cr5, L(dureturn29) ld r29,-24(r1) ld r28,-32(r1) li rRTN, -1 @@ -955,14 +955,14 @@ L(duZeroReturn): L(dureturn): ld rWORD8,-8(r1) ld rWORD7,-16(r1) -L(dureturn29): +L(dureturn29): ld r29,-24(r1) ld r28,-32(r1) -L(dureturn27): +L(dureturn27): ld r27,-40(r1) -L(dureturn26): +L(dureturn26): ld r26,-48(r1) -L(dureturn25): +L(dureturn25): ld r25,-56(r1) L(dureturn24): ld r24,-64(r1) diff --git a/sysdeps/powerpc/powerpc64/power4/memcpy.S b/sysdeps/powerpc/powerpc64/power4/memcpy.S index c43d1d2..4317c7e 100644 --- a/sysdeps/powerpc/powerpc64/power4/memcpy.S +++ b/sysdeps/powerpc/powerpc64/power4/memcpy.S @@ -21,10 +21,10 @@ /* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]); Returns 'dst'. - Memcpy handles short copies (< 32-bytes) using a binary move blocks - (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled - with the appropriate combination of byte and halfword load/stores. - There is minimal effort to optimize the alignment of short moves. + Memcpy handles short copies (< 32-bytes) using a binary move blocks + (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled + with the appropriate combination of byte and halfword load/stores. + There is minimal effort to optimize the alignment of short moves. The 64-bit implementations of POWER3 and POWER4 do a reasonable job of handling unaligned load/stores that do not cross 32-byte boundaries. @@ -47,13 +47,13 @@ EALIGN (memcpy, 5, 0) clrldi 10,4,61 /* check alignment of src. */ cmpldi cr6,5,8 ble- cr1,.L2 /* If move < 32 bytes use short move code. */ - cmpld cr6,10,11 + cmpld cr6,10,11 mr 12,4 srdi 9,5,3 /* Number of full double words remaining. */ mtcrf 0x01,0 mr 31,5 beq .L0 - + subf 31,0,5 /* Move 0-7 bytes as needed to get the destination doubleword aligned. */ 1: bf 31,2f @@ -74,15 +74,15 @@ EALIGN (memcpy, 5, 0) 0: clrldi 10,12,61 /* check alignment of src again. */ srdi 9,31,3 /* Number of full double words remaining. */ - + /* Copy doublewords from source to destination, assuming the destination is aligned on a doubleword boundary. At this point we know there are at least 25 bytes left (32-7) to copy. - The next step is to determine if the source is also doubleword aligned. + The next step is to determine if the source is also doubleword aligned. If not branch to the unaligned move code at .L6. which uses a load, shift, store strategy. - + Otherwise source and destination are doubleword aligned, and we can the optimized doubleword copy loop. */ .L0: @@ -95,14 +95,14 @@ EALIGN (memcpy, 5, 0) Use a unrolled loop to copy 4 doubleword (32-bytes) per iteration. If the copy is not an exact multiple of 32 bytes, 1-3 doublewords are copied as needed to set up the main loop. After - the main loop exits there may be a tail of 1-7 bytes. These byte are + the main loop exits there may be a tail of 1-7 bytes. These byte are copied a word/halfword/byte at a time as needed to preserve alignment. */ srdi 8,31,5 cmpldi cr1,9,4 cmpldi cr6,11,0 mr 11,12 - + bf 30,1f ld 6,0(12) ld 7,8(12) @@ -113,7 +113,7 @@ EALIGN (memcpy, 5, 0) addi 10,3,16 bf 31,4f ld 0,16(12) - std 0,16(3) + std 0,16(3) blt cr1,3f addi 11,12,24 addi 10,3,24 @@ -127,7 +127,7 @@ EALIGN (memcpy, 5, 0) addi 11,12,8 std 6,0(3) addi 10,3,8 - + .align 4 4: ld 6,0(11) @@ -142,7 +142,7 @@ EALIGN (memcpy, 5, 0) std 0,24(10) addi 10,10,32 bdnz 4b -3: +3: rldicr 0,31,0,60 mtcrf 0x01,31 @@ -150,7 +150,7 @@ EALIGN (memcpy, 5, 0) .L9: add 3,3,0 add 12,12,0 - + /* At this point we have a tail of 0-7 bytes and we know that the destination is double word aligned. */ 4: bf 29,2f @@ -171,29 +171,29 @@ EALIGN (memcpy, 5, 0) ld 31,-8(1) ld 3,-16(1) blr - -/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 - bytes. Each case is handled without loops, using binary (1,2,4,8) - tests. - + +/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 + bytes. Each case is handled without loops, using binary (1,2,4,8) + tests. + In the short (0-8 byte) case no attempt is made to force alignment - of either source or destination. The hardware will handle the - unaligned load/stores with small delays for crossing 32- 64-byte, and + of either source or destination. The hardware will handle the + unaligned load/stores with small delays for crossing 32- 64-byte, and 4096-byte boundaries. Since these short moves are unlikely to be - unaligned or cross these boundaries, the overhead to force + unaligned or cross these boundaries, the overhead to force alignment is not justified. - + The longer (9-31 byte) move is more likely to cross 32- or 64-byte boundaries. Since only loads are sensitive to the 32-/64-byte - boundaries it is more important to align the source then the + boundaries it is more important to align the source then the destination. If the source is not already word aligned, we first - move 1-3 bytes as needed. Since we are only word aligned we don't - use double word load/stores to insure that all loads are aligned. + move 1-3 bytes as needed. Since we are only word aligned we don't + use double word load/stores to insure that all loads are aligned. While the destination and stores may still be unaligned, this is only an issue for page (4096 byte boundary) crossing, which should be rare for these short moves. The hardware handles this - case automatically with a small delay. */ - + case automatically with a small delay. */ + .align 4 .L2: mtcrf 0x01,5 @@ -256,11 +256,11 @@ EALIGN (memcpy, 5, 0) lwz 6,0(12) addi 12,12,4 stw 6,0(3) - addi 3,3,4 + addi 3,3,4 2: /* Move 2-3 bytes. */ bf 30,1f lhz 6,0(12) - sth 6,0(3) + sth 6,0(3) bf 31,0f lbz 7,2(12) stb 7,2(3) @@ -281,7 +281,7 @@ EALIGN (memcpy, 5, 0) mr 12,4 bne cr6,4f /* Would have liked to use use ld/std here but the 630 processors are - slow for load/store doubles that are not at least word aligned. + slow for load/store doubles that are not at least word aligned. Unaligned Load/Store word execute with only a 1 cycle penalty. */ lwz 6,0(4) lwz 7,4(4) @@ -297,14 +297,14 @@ EALIGN (memcpy, 5, 0) 6: bf 30,5f lhz 7,4(4) - sth 7,4(3) + sth 7,4(3) bf 31,0f lbz 8,6(4) stb 8,6(3) ld 3,-16(1) blr .align 4 -5: +5: bf 31,0f lbz 6,4(4) stb 6,4(3) @@ -401,7 +401,7 @@ EALIGN (memcpy, 5, 0) /* calculate and store the final DW */ sld 0,6,10 srd 8,7,9 - or 0,0,8 + or 0,0,8 std 0,0(4) 3: rldicr 0,31,0,60 diff --git a/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S b/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S index 108910e..28df006 100644 --- a/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S @@ -18,13 +18,13 @@ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long long [r3] llround (float x [fp1]) - IEEE 1003.1 llround function. IEEE specifies "round to the nearest + IEEE 1003.1 llround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use Floating Convert to Integer Word with round to zero instruction. */ @@ -32,7 +32,7 @@ .machine "power5" EALIGN (__llround, 4, 0) CALL_MCOUNT 0 - frin fp2, fp1 /* Round to nearest +-0.5. */ + frin fp2, fp1 /* Round to nearest +-0.5. */ fctidz fp3, fp2 /* Convert To Integer DW round toward 0. */ stfd fp3, -16(r1) nop /* Insure the following load is in a different dispatch group */ diff --git a/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S index 3afec2b..8319d6e 100644 --- a/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S @@ -21,13 +21,13 @@ /* int __isnan(x) */ .machine power5 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 stfd fp1,-8(r1) /* copy FPR to GPR */ lis r0,0x7ff0 nop /* insure the following is in a different */ nop /* dispatch group */ - ld r4,-8(r1) + ld r4,-8(r1) sldi r0,r0,32 /* const long r0 0x7ff00000 00000000 */ clrldi r4,r4,1 /* x = fabs(x) */ cmpd cr7,r4,r0 /* if (fabs(x) <= inf) */ diff --git a/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S index 8f0c806..d4515d6 100644 --- a/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S @@ -21,7 +21,7 @@ /* int __isnan(x) */ .machine power6 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 stfd fp1,-8(r1) /* copy FPR to GPR */ ori r1,r1,0 diff --git a/sysdeps/powerpc/powerpc64/power6/memcpy.S b/sysdeps/powerpc/powerpc64/power6/memcpy.S index 55c0d71..db29e2b 100644 --- a/sysdeps/powerpc/powerpc64/power6/memcpy.S +++ b/sysdeps/powerpc/powerpc64/power6/memcpy.S @@ -21,22 +21,22 @@ /* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]); Returns 'dst'. - Memcpy handles short copies (< 32-bytes) using a binary move blocks - (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled - with the appropriate combination of byte and halfword load/stores. - There is minimal effort to optimize the alignment of short moves. + Memcpy handles short copies (< 32-bytes) using a binary move blocks + (no loops) of lwz/stw. The tail (remaining 1-3) bytes is handled + with the appropriate combination of byte and halfword load/stores. + There is minimal effort to optimize the alignment of short moves. The 64-bit implementations of POWER3 and POWER4 do a reasonable job of handling unaligned load/stores that do not cross 32-byte boundaries. Longer moves (>= 32-bytes) justify the effort to get at least the destination doubleword (8-byte) aligned. Further optimization is possible when both source and destination are doubleword aligned. - Each case has a optimized unrolled loop. - + Each case has a optimized unrolled loop. + For POWER6 unaligned loads will take a 20+ cycle hiccup for any L1 cache miss that crosses a 32- or 128-byte boundary. Store is more forgiving and does not take a hiccup until page or - segment boundaries. So we require doubleword alignment for + segment boundaries. So we require doubleword alignment for the source but may take a risk and only require word alignment for the destination. */ @@ -54,10 +54,10 @@ EALIGN (memcpy, 7, 0) cmpldi cr6,5,8 ble- cr1,.L2 /* If move < 32 bytes use short move code. */ mtcrf 0x01,0 - cmpld cr6,10,11 + cmpld cr6,10,11 srdi 9,5,3 /* Number of full double words remaining. */ beq .L0 - + subf 5,0,5 /* Move 0-7 bytes as needed to get the destination doubleword aligned. Duplicate some code to maximize fall-through and minimize agen delays. */ @@ -76,7 +76,7 @@ EALIGN (memcpy, 7, 0) lwz 6,1(4) stw 6,1(3) b 0f - + 2: bf 30,4f lhz 6,0(4) sth 6,0(3) @@ -84,26 +84,26 @@ EALIGN (memcpy, 7, 0) lwz 6,2(4) stw 6,2(3) b 0f - + 4: bf 29,0f lwz 6,0(4) stw 6,0(3) -0: +0: /* Add the number of bytes until the 1st doubleword of dst to src and dst. */ add 4,4,0 add 3,3,0 - + clrldi 10,4,61 /* check alignment of src again. */ srdi 9,5,3 /* Number of full double words remaining. */ - + /* Copy doublewords from source to destination, assuming the destination is aligned on a doubleword boundary. At this point we know there are at least 25 bytes left (32-7) to copy. - The next step is to determine if the source is also doubleword aligned. + The next step is to determine if the source is also doubleword aligned. If not branch to the unaligned move code at .L6. which uses a load, shift, store strategy. - + Otherwise source and destination are doubleword aligned, and we can the optimized doubleword copy loop. */ .align 4 @@ -121,12 +121,12 @@ EALIGN (memcpy, 7, 0) the main loop exits there may be a tail of 1-7 bytes. These byte are copied a word/halfword/byte at a time as needed to preserve alignment. - + For POWER6 the L1 is store-through and the L2 is store-in. The L2 is clocked at half CPU clock so we can store 16 bytes every other cycle. POWER6 also has a load/store bypass so we can do - load, load, store, store every 2 cycles. - + load, load, store, store every 2 cycles. + The following code is sensitive to cache line alignment. Do not make any change with out first making sure they don't result in splitting ld/std pairs across a cache line. */ @@ -271,7 +271,7 @@ L(das_loop): std 8,16+96(10) std 0,24+96(10) ble cr5,L(das_loop_e) - + mtctr 12 .align 4 L(das_loop2): @@ -324,7 +324,7 @@ L(das_loop_e): .align 4 L(das_tail): beq cr1,0f - + L(das_tail2): /* At this point we have a tail of 0-7 bytes and we know that the destination is double word aligned. */ @@ -342,7 +342,7 @@ L(das_tail2): lbz 6,4(4) stb 6,4(3) b 0f - + 2: bf 30,1f lhz 6,0(4) sth 6,0(3) @@ -350,7 +350,7 @@ L(das_tail2): lbz 6,2(4) stb 6,2(3) b 0f - + 1: bf 31,0f lbz 6,0(4) stb 6,0(3) @@ -359,7 +359,7 @@ L(das_tail2): ld 3,-16(1) blr -/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 +/* Copy up to 31 bytes. This divided into two cases 0-8 bytes and 9-31 bytes. Each case is handled without loops, using binary (1,2,4,8) tests. @@ -419,7 +419,7 @@ L(dus_tail): /* At least 6 bytes left and the source is word aligned. This allows some speculative loads up front. */ /* We need to special case the fall-through because the biggest delays - are due to address computation not being ready in time for the + are due to address computation not being ready in time for the AGEN. */ lwz 6,0(12) lwz 7,4(12) @@ -515,7 +515,7 @@ L(dus_tail4): /* Move 4 bytes. */ L(dus_tail2): /* Move 2-3 bytes. */ bf 30,L(dus_tail1) lhz 6,0(12) - sth 6,0(3) + sth 6,0(3) bf 31,L(dus_tailX) lbz 7,2(12) stb 7,2(3) @@ -550,7 +550,7 @@ L(dus_4): stw 6,0(3) bf 30,L(dus_5) lhz 7,4(4) - sth 7,4(3) + sth 7,4(3) bf 31,L(dus_0) lbz 8,6(4) stb 8,6(3) @@ -588,8 +588,8 @@ L(dus_0): bge cr0, L(du4_do) blt cr5, L(du1_do) beq cr5, L(du2_do) - b L(du3_do) - + b L(du3_do) + .align 4 L(du1_do): bf 30,L(du1_1dw) @@ -663,7 +663,7 @@ L(du1_fini): /* calculate and store the final DW */ sldi 0,6, 8 srdi 8,7, 64-8 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -740,7 +740,7 @@ L(du2_fini): /* calculate and store the final DW */ sldi 0,6, 16 srdi 8,7, 64-16 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -817,7 +817,7 @@ L(du3_fini): /* calculate and store the final DW */ sldi 0,6, 24 srdi 8,7, 64-24 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -900,7 +900,7 @@ L(du4_fini): /* calculate and store the final DW */ sldi 0,6, 32 srdi 8,7, 64-32 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -977,7 +977,7 @@ L(du5_fini): /* calculate and store the final DW */ sldi 0,6, 40 srdi 8,7, 64-40 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -1054,7 +1054,7 @@ L(du6_fini): /* calculate and store the final DW */ sldi 0,6, 48 srdi 8,7, 64-48 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) @@ -1131,10 +1131,10 @@ L(du7_fini): /* calculate and store the final DW */ sldi 0,6, 56 srdi 8,7, 64-56 - or 0,0,8 + or 0,0,8 std 0,0(4) b L(du_done) - + .align 4 L(du_done): rldicr 0,31,0,60 @@ -1142,7 +1142,7 @@ L(du_done): beq cr1,0f /* If the tail is 0 bytes we are done! */ add 3,3,0 - add 12,12,0 + add 12,12,0 /* At this point we have a tail of 0-7 bytes and we know that the destination is double word aligned. */ 4: bf 29,2f diff --git a/sysdeps/powerpc/powerpc64/power6/wordcopy.c b/sysdeps/powerpc/powerpc64/power6/wordcopy.c index f19829c..7517893 100644 --- a/sysdeps/powerpc/powerpc64/power6/wordcopy.c +++ b/sysdeps/powerpc/powerpc64/power6/wordcopy.c @@ -37,7 +37,7 @@ _wordcopy_fwd_aligned (dstp, srcp, len) if (len & 1) { ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; srcp += OPSIZ; @@ -105,10 +105,10 @@ _wordcopy_fwd_dest_aligned (dstp, srcp, len) { a1 = ((op_t *) srcp)[1]; ((op_t *) dstp)[0] = MERGE (a0, sh_1, a1, sh_2); - + if (len == 1) return; - + a0 = a1; srcp += OPSIZ; dstp += OPSIZ; @@ -137,7 +137,7 @@ _wordcopy_bwd_aligned (dstp, srcp, len) srcp -= OPSIZ; dstp -= OPSIZ; ((op_t *) dstp)[0] = ((op_t *) srcp)[0]; - + if (len == 1) return; len -= 1; diff --git a/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S b/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S index c09eb65..d29fe9e 100644 --- a/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S +++ b/sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S @@ -21,7 +21,7 @@ /* int __isnan(x) */ .machine power6 -EALIGN (__isnan, 4, 0) +EALIGN (__isnan, 4, 0) CALL_MCOUNT 0 mftgpr r4,fp1 /* copy FPR to GPR */ lis r0,0x7ff0 diff --git a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S index bb1627f..67d51ad 100644 --- a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S +++ b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S @@ -21,7 +21,7 @@ .machine "power6" /* long long int[r3] __llrint (double x[fp1]) */ -ENTRY (__llrint) +ENTRY (__llrint) CALL_MCOUNT 0 fctid fp13,fp1 mftgpr r3,fp13 diff --git a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S index 902db67..45aacea 100644 --- a/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S +++ b/sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S @@ -18,13 +18,13 @@ #include <sysdep.h> #include <math_ldbl_opt.h> - + /* long long [r3] llround (float x [fp1]) - IEEE 1003.1 llround function. IEEE specifies "round to the nearest + IEEE 1003.1 llround function. IEEE specifies "round to the nearest integer value, rounding halfway cases away from zero, regardless of the current rounding mode." However PowerPC Architecture defines - "round to Nearest" as "Choose the best approximation. In case of a - tie, choose the one that is even (least significant bit o).". + "round to Nearest" as "Choose the best approximation. In case of a + tie, choose the one that is even (least significant bit o).". So we pre-round using the V2.02 Floating Round to Integer Nearest instruction before we use Floating Convert to Integer Word with round to zero instruction. */ @@ -32,7 +32,7 @@ .machine "power6" ENTRY (__llround) CALL_MCOUNT 0 - frin fp2,fp1 /* Round to nearest +-0.5. */ + frin fp2,fp1 /* Round to nearest +-0.5. */ fctidz fp3,fp2 /* Convert To Integer DW round toward 0. */ mftgpr r3,fp3 /* Transfer integer to R3. */ blr diff --git a/sysdeps/powerpc/powerpc64/strlen.S b/sysdeps/powerpc/powerpc64/strlen.S index dafd033..0f9b5ee 100644 --- a/sysdeps/powerpc/powerpc64/strlen.S +++ b/sysdeps/powerpc/powerpc64/strlen.S @@ -57,11 +57,11 @@ 2) How popular are bytes with the high bit set? If they are very rare, on some processors it might be useful to use the simpler expression ~((x - 0x01010101) | 0x7f7f7f7f) (that is, on processors with only one - ALU), but this fails when any character has its high bit set. - + ALU), but this fails when any character has its high bit set. + Answer: - 1) Added a Data Cache Block Touch early to prefetch the first 128 - byte cache line. Adding dcbt instructions to the loop would not be + 1) Added a Data Cache Block Touch early to prefetch the first 128 + byte cache line. Adding dcbt instructions to the loop would not be effective since most strings will be shorter than the cache line.*/ /* Some notes on register usage: Under the SVR4 ABI, we can use registers @@ -101,7 +101,7 @@ ENTRY (strlen) li rMASK, -1 insrdi r7F7F, r7F7F, 32, 0 /* That's the setup done, now do the first pair of doublewords. - We make an exception and use method (2) on the first two doublewords, + We make an exception and use method (2) on the first two doublewords, to reduce overhead. */ srd rMASK, rMASK, rPADN and rTMP1, r7F7F, rWORD1 diff --git a/sysdeps/powerpc/powerpc64/strncmp.S b/sysdeps/powerpc/powerpc64/strncmp.S index e272688..779d9f7 100644 --- a/sysdeps/powerpc/powerpc64/strncmp.S +++ b/sysdeps/powerpc/powerpc64/strncmp.S @@ -51,7 +51,7 @@ EALIGN (strncmp, 4, 0) clrldi rN, rN, 61 addi rFEFE, rFEFE, -0x101 addi r7F7F, r7F7F, 0x7f7f - cmpldi cr1, rN, 0 + cmpldi cr1, rN, 0 beq L(unaligned) mtctr rTMP /* Power4 wants mtctr 1st in dispatch group. */ @@ -62,7 +62,7 @@ EALIGN (strncmp, 4, 0) add rFEFE, rFEFE, rTMP b L(g1) -L(g0): +L(g0): ldu rWORD1, 8(rSTR1) bne- cr1, L(different) ldu rWORD2, 8(rSTR2) @@ -72,11 +72,11 @@ L(g1): add rTMP, rFEFE, rWORD1 and. rTMP, rTMP, rNEG cmpd cr1, rWORD1, rWORD2 beq+ L(g0) - + /* OK. We've hit the end of the string. We need to be careful that we don't compare two strings as different because of gunk beyond the end of the strings... */ - + L(endstring): and rTMP, r7F7F, rWORD1 beq cr1, L(equal) @@ -152,7 +152,7 @@ L(u1): lbzu rWORD1, 1(rSTR1) bne+ cr1, L(u0) -L(u2): lbzu rWORD1, -1(rSTR1) +L(u2): lbzu rWORD1, -1(rSTR1) L(u3): sub rRTN, rWORD1, rWORD2 blr END (strncmp) diff --git a/sysdeps/powerpc/sysdep.h b/sysdeps/powerpc/sysdep.h index a2ed88f..1b5334a 100644 --- a/sysdeps/powerpc/sysdep.h +++ b/sysdeps/powerpc/sysdep.h @@ -15,8 +15,8 @@ License along with the GNU C Library; if not, see <http://www.gnu.org/licenses/>. */ -/* - * Powerpc Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP). +/* + * Powerpc Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP). * This entry is copied to _dl_hwcap or rtld_global._dl_hwcap during startup. */ #define _SYS_AUXV_H 1 diff --git a/sysdeps/s390/s390-64/s390x-mcount.S b/sysdeps/s390/s390-64/s390x-mcount.S index 699770d..66ec9e6 100644 --- a/sysdeps/s390/s390-64/s390x-mcount.S +++ b/sysdeps/s390/s390-64/s390x-mcount.S @@ -23,10 +23,10 @@ On the start of each function _mcount is called with the address of a data word in %r1 (initialized to 0, used for counting). The compiler with the option -p generates code of the form: - + STM 6,15,24(15) BRAS 13,.LTN0_0 - .LT0_0: + .LT0_0: .LC13: .long .LP0 .data .align 4 @@ -37,7 +37,7 @@ lg 1,.LC13-.LT0_0(13) brasl 14,_mcount lg 14,4(15) - + The _mcount implementation now has to call __mcount_internal with the address of .LP0 as first parameter and the return address as second parameter. &.LP0 was loaded to %r1 and the return address is in %r14. diff --git a/sysdeps/s390/s390-64/sub_n.S b/sysdeps/s390/s390-64/sub_n.S index 0f7ea92..9f1f670 100644 --- a/sysdeps/s390/s390-64/sub_n.S +++ b/sysdeps/s390/s390-64/sub_n.S @@ -23,7 +23,7 @@ %r3 = s1_ptr %r4 = s2_ptr %r5 = size. */ - + #include "sysdep.h" #include "asm-syntax.h" diff --git a/sysdeps/sh/dl-trampoline.S b/sysdeps/sh/dl-trampoline.S index ab3371c..c0d2fba 100644 --- a/sysdeps/sh/dl-trampoline.S +++ b/sysdeps/sh/dl-trampoline.S @@ -299,7 +299,7 @@ _dl_runtime_profile: mov r15,r4 shlr2 r1 tst r1,r1 -5: +5: bt/s 6f dt r1 mov.l @r3+,r2 diff --git a/sysdeps/sh/memset.S b/sysdeps/sh/memset.S index 8c24d8d..e61238c 100644 --- a/sysdeps/sh/memset.S +++ b/sysdeps/sh/memset.S @@ -38,7 +38,7 @@ ENTRY(memset) bt L_wordalign mov.b r5,@r4 - add #-1,r6 + add #-1,r6 add #1,r4 mov r4,r0 diff --git a/sysdeps/sh/sh4/fpu/fclrexcpt.c b/sysdeps/sh/sh4/fpu/fclrexcpt.c index 56d3743..8525bcd 100644 --- a/sysdeps/sh/sh4/fpu/fclrexcpt.c +++ b/sysdeps/sh/sh4/fpu/fclrexcpt.c @@ -33,7 +33,7 @@ feclearexcept (int excepts) /* Clear exception bits. */ cw &= ~excepts; - + /* Put the new data in effect. */ _FPU_SETCW (cw); diff --git a/sysdeps/sh/strlen.S b/sysdeps/sh/strlen.S index eaf2d3b..97ef06c 100644 --- a/sysdeps/sh/strlen.S +++ b/sysdeps/sh/strlen.S @@ -36,17 +36,17 @@ ENTRY(strlen) mov.b @r4+, r1 tst r1, r1 bt 8f - add #1, r2 + add #1, r2 mov.b @r4+, r1 tst r1, r1 bt 8f - add #1, r2 + add #1, r2 mov.b @r4+, r1 tst r1, r1 bt 8f - add #1, r2 + add #1, r2 1: mov #0, r3 diff --git a/sysdeps/sparc/sparc32/dl-trampoline.S b/sysdeps/sparc/sparc32/dl-trampoline.S index 723c4f0..2599cd7 100644 --- a/sysdeps/sparc/sparc32/dl-trampoline.S +++ b/sysdeps/sparc/sparc32/dl-trampoline.S @@ -175,7 +175,7 @@ _dl_runtime_profile: cmp %l0, 0 bl 1f nop - + call _dl_profile_invoke nop diff --git a/sysdeps/sparc/sparc32/dotmul.S b/sysdeps/sparc/sparc32/dotmul.S index 821aa8b..d497ca6 100644 --- a/sysdeps/sparc/sparc32/dotmul.S +++ b/sysdeps/sparc/sparc32/dotmul.S @@ -65,7 +65,7 @@ ENTRY(.mul) bge 1f rd %y, %o0 - ! %o0 was indeed negative; fix upper 32 bits of result by subtracting + ! %o0 was indeed negative; fix upper 32 bits of result by subtracting ! %o1 (i.e., return %o4 - %o1 in %o1). retl sub %o4, %o1, %o1 @@ -79,7 +79,7 @@ ENTRY(.mul) and %o1, %o2, %o2 ! %o2 = 0 or %o1, depending on sign of %o0 rd %y, %o0 ! get lower half of product retl - sub %o4, %o2, %o1 ! subtract compensation + sub %o4, %o2, %o1 ! subtract compensation ! and put upper half in place #endif diff --git a/sysdeps/sparc/sparc32/memcpy.S b/sysdeps/sparc/sparc32/memcpy.S index 98536fb..d8fbd2e 100644 --- a/sysdeps/sparc/sparc32/memcpy.S +++ b/sysdeps/sparc/sparc32/memcpy.S @@ -306,7 +306,7 @@ ENTRY(memcpy) /* %o0=dst %o1=src %o2=len */ mov 32, %g2 be 4f sub %g2, %g4, %g6 - + blu 3f cmp %g3, 0x8 @@ -539,7 +539,7 @@ ENTRY(memcpy) /* %o0=dst %o1=src %o2=len */ add %o1, 64, %o1 bne 41b add %o0, 64, %o0 - + andcc %o2, 0x30, %o3 be,a 1f srl %g1, 16, %g2 @@ -584,7 +584,7 @@ ENTRY(memcpy) /* %o0=dst %o1=src %o2=len */ add %o1, 64, %o1 bne 42b add %o0, 64, %o0 - + andcc %o2, 0x30, %o3 be,a 1f srl %g1, 16, %g2 @@ -598,7 +598,7 @@ ENTRY(memcpy) /* %o0=dst %o1=src %o2=len */ 1: sth %g2, [%o0 - 2] /* Fall through */ - + 88: and %o2, 0xe, %o3 mov %o7, %g2 sll %o3, 3, %o4 diff --git a/sysdeps/sparc/sparc32/rem.S b/sysdeps/sparc/sparc32/rem.S index effacee..349d7c0 100644 --- a/sysdeps/sparc/sparc32/rem.S +++ b/sysdeps/sparc/sparc32/rem.S @@ -181,14 +181,14 @@ LOC(divloop): subcc %o3,%o5,%o3 b 9f add %o2, (7*2+1), %o2 - + LOC(4.23): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (7*2-1), %o2 - - + + LOC(3.19): ! remainder is negative addcc %o3,%o5,%o3 @@ -199,15 +199,15 @@ LOC(3.19): subcc %o3,%o5,%o3 b 9f add %o2, (5*2+1), %o2 - + LOC(4.21): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (5*2-1), %o2 - - - + + + LOC(2.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -223,14 +223,14 @@ LOC(2.17): subcc %o3,%o5,%o3 b 9f add %o2, (3*2+1), %o2 - + LOC(4.19): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (3*2-1), %o2 - - + + LOC(3.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -241,16 +241,16 @@ LOC(3.17): subcc %o3,%o5,%o3 b 9f add %o2, (1*2+1), %o2 - + LOC(4.17): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (1*2-1), %o2 - - - - + + + + LOC(1.16): ! remainder is negative addcc %o3,%o5,%o3 @@ -271,14 +271,14 @@ LOC(1.16): subcc %o3,%o5,%o3 b 9f add %o2, (-1*2+1), %o2 - + LOC(4.15): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-1*2-1), %o2 - - + + LOC(3.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -289,15 +289,15 @@ LOC(3.15): subcc %o3,%o5,%o3 b 9f add %o2, (-3*2+1), %o2 - + LOC(4.13): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-3*2-1), %o2 - - - + + + LOC(2.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -313,14 +313,14 @@ LOC(2.15): subcc %o3,%o5,%o3 b 9f add %o2, (-5*2+1), %o2 - + LOC(4.11): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-5*2-1), %o2 - - + + LOC(3.13): ! remainder is negative addcc %o3,%o5,%o3 @@ -331,16 +331,16 @@ LOC(3.13): subcc %o3,%o5,%o3 b 9f add %o2, (-7*2+1), %o2 - + LOC(4.9): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-7*2-1), %o2 - - - - + + + + 9: LOC(end_regular_divide): subcc %o4, 1, %o4 diff --git a/sysdeps/sparc/sparc32/sdiv.S b/sysdeps/sparc/sparc32/sdiv.S index 4b32547..d1d4ee3 100644 --- a/sysdeps/sparc/sparc32/sdiv.S +++ b/sysdeps/sparc/sparc32/sdiv.S @@ -181,14 +181,14 @@ LOC(divloop): subcc %o3,%o5,%o3 b 9f add %o2, (7*2+1), %o2 - + LOC(4.23): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (7*2-1), %o2 - - + + LOC(3.19): ! remainder is negative addcc %o3,%o5,%o3 @@ -199,15 +199,15 @@ LOC(3.19): subcc %o3,%o5,%o3 b 9f add %o2, (5*2+1), %o2 - + LOC(4.21): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (5*2-1), %o2 - - - + + + LOC(2.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -223,14 +223,14 @@ LOC(2.17): subcc %o3,%o5,%o3 b 9f add %o2, (3*2+1), %o2 - + LOC(4.19): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (3*2-1), %o2 - - + + LOC(3.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -241,16 +241,16 @@ LOC(3.17): subcc %o3,%o5,%o3 b 9f add %o2, (1*2+1), %o2 - + LOC(4.17): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (1*2-1), %o2 - - - - + + + + LOC(1.16): ! remainder is negative addcc %o3,%o5,%o3 @@ -271,14 +271,14 @@ LOC(1.16): subcc %o3,%o5,%o3 b 9f add %o2, (-1*2+1), %o2 - + LOC(4.15): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-1*2-1), %o2 - - + + LOC(3.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -289,15 +289,15 @@ LOC(3.15): subcc %o3,%o5,%o3 b 9f add %o2, (-3*2+1), %o2 - + LOC(4.13): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-3*2-1), %o2 - - - + + + LOC(2.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -313,14 +313,14 @@ LOC(2.15): subcc %o3,%o5,%o3 b 9f add %o2, (-5*2+1), %o2 - + LOC(4.11): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-5*2-1), %o2 - - + + LOC(3.13): ! remainder is negative addcc %o3,%o5,%o3 @@ -331,16 +331,16 @@ LOC(3.13): subcc %o3,%o5,%o3 b 9f add %o2, (-7*2+1), %o2 - + LOC(4.9): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-7*2-1), %o2 - - - - + + + + 9: LOC(end_regular_divide): subcc %o4, 1, %o4 diff --git a/sysdeps/sparc/sparc32/soft-fp/q_neg.c b/sysdeps/sparc/sparc32/soft-fp/q_neg.c index 3101555..551c408 100644 --- a/sysdeps/sparc/sparc32/soft-fp/q_neg.c +++ b/sysdeps/sparc/sparc32/soft-fp/q_neg.c @@ -26,7 +26,7 @@ long double _Q_neg(const long double a) { FP_DECL_EX; long double c = a; - + #if (__BYTE_ORDER == __BIG_ENDIAN) ((UWtype *)&c)[0] ^= (((UWtype)1) << (W_TYPE_SIZE - 1)); #elif (__BYTE_ORDER == __LITTLE_ENDIAN) && (W_TYPE_SIZE == 64) diff --git a/sysdeps/sparc/sparc32/strchr.S b/sysdeps/sparc/sparc32/strchr.S index 9dafe83..f80e77b 100644 --- a/sysdeps/sparc/sparc32/strchr.S +++ b/sysdeps/sparc/sparc32/strchr.S @@ -92,13 +92,13 @@ ENTRY(strchr) #else sub %g5, %o2, %g5 #endif - or %g5, %o4, %o4 + or %g5, %o4, %o4 andcc %o4, %o3, %g0 be 7b add %o0, 4, %o0 /* Check every byte. */ -8: srl %g4, 24, %g5 +8: srl %g4, 24, %g5 7: andcc %g5, 0xff, %g5 be 9f cmp %g5, %o1 @@ -243,13 +243,13 @@ ENTRY(strrchr) #else sub %g5, %o2, %g5 #endif - or %g5, %o4, %o4 + or %g5, %o4, %o4 andcc %o4, %o3, %g0 be 6b add %o0, 4, %o0 /* Check every byte. */ -3: srl %g4, 24, %g5 +3: srl %g4, 24, %g5 8: andcc %g5, 0xff, %g5 be 9f cmp %g5, %o1 diff --git a/sysdeps/sparc/sparc32/udiv.S b/sysdeps/sparc/sparc32/udiv.S index 0dd48f3..8dfff66 100644 --- a/sysdeps/sparc/sparc32/udiv.S +++ b/sysdeps/sparc/sparc32/udiv.S @@ -168,14 +168,14 @@ LOC(divloop): subcc %o3,%o5,%o3 b 9f add %o2, (7*2+1), %o2 - + LOC(4.23): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (7*2-1), %o2 - - + + LOC(3.19): ! remainder is negative addcc %o3,%o5,%o3 @@ -186,15 +186,15 @@ LOC(3.19): subcc %o3,%o5,%o3 b 9f add %o2, (5*2+1), %o2 - + LOC(4.21): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (5*2-1), %o2 - - - + + + LOC(2.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -210,14 +210,14 @@ LOC(2.17): subcc %o3,%o5,%o3 b 9f add %o2, (3*2+1), %o2 - + LOC(4.19): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (3*2-1), %o2 - - + + LOC(3.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -228,16 +228,16 @@ LOC(3.17): subcc %o3,%o5,%o3 b 9f add %o2, (1*2+1), %o2 - + LOC(4.17): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (1*2-1), %o2 - - - - + + + + LOC(1.16): ! remainder is negative addcc %o3,%o5,%o3 @@ -258,14 +258,14 @@ LOC(1.16): subcc %o3,%o5,%o3 b 9f add %o2, (-1*2+1), %o2 - + LOC(4.15): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-1*2-1), %o2 - - + + LOC(3.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -276,15 +276,15 @@ LOC(3.15): subcc %o3,%o5,%o3 b 9f add %o2, (-3*2+1), %o2 - + LOC(4.13): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-3*2-1), %o2 - - - + + + LOC(2.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -300,14 +300,14 @@ LOC(2.15): subcc %o3,%o5,%o3 b 9f add %o2, (-5*2+1), %o2 - + LOC(4.11): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-5*2-1), %o2 - - + + LOC(3.13): ! remainder is negative addcc %o3,%o5,%o3 @@ -318,16 +318,16 @@ LOC(3.13): subcc %o3,%o5,%o3 b 9f add %o2, (-7*2+1), %o2 - + LOC(4.9): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-7*2-1), %o2 - - - - + + + + 9: LOC(end_regular_divide): subcc %o4, 1, %o4 diff --git a/sysdeps/sparc/sparc32/urem.S b/sysdeps/sparc/sparc32/urem.S index 5644e7a..d3a1a44 100644 --- a/sysdeps/sparc/sparc32/urem.S +++ b/sysdeps/sparc/sparc32/urem.S @@ -168,14 +168,14 @@ LOC(divloop): subcc %o3,%o5,%o3 b 9f add %o2, (7*2+1), %o2 - + LOC(4.23): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (7*2-1), %o2 - - + + LOC(3.19): ! remainder is negative addcc %o3,%o5,%o3 @@ -186,15 +186,15 @@ LOC(3.19): subcc %o3,%o5,%o3 b 9f add %o2, (5*2+1), %o2 - + LOC(4.21): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (5*2-1), %o2 - - - + + + LOC(2.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -210,14 +210,14 @@ LOC(2.17): subcc %o3,%o5,%o3 b 9f add %o2, (3*2+1), %o2 - + LOC(4.19): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (3*2-1), %o2 - - + + LOC(3.17): ! remainder is negative addcc %o3,%o5,%o3 @@ -228,16 +228,16 @@ LOC(3.17): subcc %o3,%o5,%o3 b 9f add %o2, (1*2+1), %o2 - + LOC(4.17): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (1*2-1), %o2 - - - - + + + + LOC(1.16): ! remainder is negative addcc %o3,%o5,%o3 @@ -258,14 +258,14 @@ LOC(1.16): subcc %o3,%o5,%o3 b 9f add %o2, (-1*2+1), %o2 - + LOC(4.15): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-1*2-1), %o2 - - + + LOC(3.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -276,15 +276,15 @@ LOC(3.15): subcc %o3,%o5,%o3 b 9f add %o2, (-3*2+1), %o2 - + LOC(4.13): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-3*2-1), %o2 - - - + + + LOC(2.15): ! remainder is negative addcc %o3,%o5,%o3 @@ -300,14 +300,14 @@ LOC(2.15): subcc %o3,%o5,%o3 b 9f add %o2, (-5*2+1), %o2 - + LOC(4.11): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-5*2-1), %o2 - - + + LOC(3.13): ! remainder is negative addcc %o3,%o5,%o3 @@ -318,16 +318,16 @@ LOC(3.13): subcc %o3,%o5,%o3 b 9f add %o2, (-7*2+1), %o2 - + LOC(4.9): ! remainder is negative addcc %o3,%o5,%o3 b 9f add %o2, (-7*2-1), %o2 - - - - + + + + 9: LOC(end_regular_divide): subcc %o4, 1, %o4 diff --git a/sysdeps/sparc/sparc64/add_n.S b/sysdeps/sparc/sparc64/add_n.S index 154ffe3..ce0fcb8 100644 --- a/sysdeps/sparc/sparc64/add_n.S +++ b/sysdeps/sparc/sparc64/add_n.S @@ -1,6 +1,6 @@ /* SPARC v9 __mpn_add_n -- Add two limb vectors of the same length > 0 and store sum in a third limb vector. - + Copyright (C) 1995-2013 Free Software Foundation, Inc. This file is part of the GNU MP Library. diff --git a/sysdeps/sparc/sparc64/memcpy.S b/sysdeps/sparc/sparc64/memcpy.S index 7e03d78..3d8ffcc 100644 --- a/sysdeps/sparc/sparc64/memcpy.S +++ b/sysdeps/sparc/sparc64/memcpy.S @@ -385,7 +385,7 @@ ENTRY(memcpy) 210: #ifndef USE_BPR srl %o2, 0, %o2 /* IEU1 */ -#endif +#endif brz,pn %o2, 209b /* CTI Group */ 218: cmp %o2, 15 /* IEU1 */ bleu,pn %xcc, 208b /* CTI Group */ diff --git a/sysdeps/sparc/sparc64/rawmemchr.S b/sysdeps/sparc/sparc64/rawmemchr.S index aafc476..cc36c58 100644 --- a/sysdeps/sparc/sparc64/rawmemchr.S +++ b/sysdeps/sparc/sparc64/rawmemchr.S @@ -57,7 +57,7 @@ ENTRY(__rawmemchr) sethi %hi(0x01010101), %g1 /* IEU1 */ ldub [%o0], %o3 /* Load */ sll %o1, 8, %o4 /* IEU0 Group */ - + or %g1, %lo(0x01010101), %g1 /* IEU1 */ sllx %g1, 32, %g2 /* IEU0 Group */ or %o4, %o1, %o4 /* IEU1 */ diff --git a/sysdeps/sparc/sparc64/soft-fp/s_frexpl.c b/sysdeps/sparc/sparc64/soft-fp/s_frexpl.c index 35bc552..c34fb13 100644 --- a/sysdeps/sparc/sparc64/soft-fp/s_frexpl.c +++ b/sysdeps/sparc/sparc64/soft-fp/s_frexpl.c @@ -26,7 +26,7 @@ * arg = x*2^exp. * If arg is inf, 0.0, or NaN, then frexpl(arg,&exp) returns arg * with *exp=0. - */ + */ #include "soft-fp.h" #include "quad.h" diff --git a/sysdeps/sparc/sparc64/soft-fp/sfp-machine.h b/sysdeps/sparc/sparc64/soft-fp/sfp-machine.h index 562fdfc..f64a4be 100644 --- a/sysdeps/sparc/sparc64/soft-fp/sfp-machine.h +++ b/sysdeps/sparc/sparc64/soft-fp/sfp-machine.h @@ -19,7 +19,7 @@ You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, see <http://www.gnu.org/licenses/>. */ - + #include <fpu_control.h> #include <fenv.h> #include <stdlib.h> @@ -38,7 +38,7 @@ do { \ #ifndef _FP_MUL_MEAT_RESET_FE #define _FP_MUL_MEAT_RESET_FE _FPU_SETCW(_fcw) #endif - + #define _FP_MUL_MEAT_S(R,X,Y) \ _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y) #define _FP_MUL_MEAT_D(R,X,Y) \ @@ -140,6 +140,6 @@ do { \ #define QP_NO_EXCEPTIONS \ __asm ("fzero %%f62\n\t" \ "faddd %%f62, %%f62, %%f62" : : : "f62") - + #define QP_CLOBBER "memory", "f52", "f54", "f56", "f58", "f60", "f62" #define QP_CLOBBER_CC QP_CLOBBER , "cc" diff --git a/sysdeps/sparc/sparc64/stpncpy.S b/sysdeps/sparc/sparc64/stpncpy.S index 4f3ad27..e01ad4e 100644 --- a/sysdeps/sparc/sparc64/stpncpy.S +++ b/sysdeps/sparc/sparc64/stpncpy.S @@ -1,4 +1,4 @@ -/* stpncpy(DST, SRC, COUNT) - Copy no more than N characters of +/* stpncpy(DST, SRC, COUNT) - Copy no more than N characters of SRC to DEST, returning the address of the terminating '\0' in DEST, if any, or else DEST + N. For SPARC v9. @@ -245,7 +245,7 @@ ENTRY(__stpncpy) be,pn %XCC, 19f /* CTI */ srlx %o3, 8, %o3 /* IEU0 Group */ - stb %o3, [%o0] /* Store */ + stb %o3, [%o0] /* Store */ 59: add %o0, 1, %o2 /* IEU1 */ andcc %o3, 0xff, %g0 /* IEU1 Group */ diff --git a/sysdeps/sparc/sparc64/strncmp.S b/sysdeps/sparc/sparc64/strncmp.S index d2e1d46..22673ec 100644 --- a/sysdeps/sparc/sparc64/strncmp.S +++ b/sysdeps/sparc/sparc64/strncmp.S @@ -1,5 +1,5 @@ -/* Compare no more than N characters of S1 and S2, returning less than, - equal to or greater than zero if S1 is lexicographically less than, +/* Compare no more than N characters of S1 and S2, returning less than, + equal to or greater than zero if S1 is lexicographically less than, equal to or greater than S2. For SPARC v9. Copyright (C) 1997-2013 Free Software Foundation, Inc. @@ -140,7 +140,7 @@ ENTRY(strncmp) cmp %o2, -8 /* IEU1 */ be,pn %XCC, 4b /* CTI */ srlx %o3, 56, %o5 /* IEU0 Group */ - + andcc %o4, 0xff, %g0 /* IEU1 */ be,pn %xcc, 8f /* CTI */ subcc %o4, %o5, %o4 /* IEU1 Group */ diff --git a/sysdeps/sparc/sparc64/strncpy.S b/sysdeps/sparc/sparc64/strncpy.S index d0c30c0..74fd275 100644 --- a/sysdeps/sparc/sparc64/strncpy.S +++ b/sysdeps/sparc/sparc64/strncpy.S @@ -227,7 +227,7 @@ ENTRY(strncpy) subcc %o2, 1, %o2 /* IEU1 */ be,pn %XCC, 19f /* CTI */ srlx %o3, 16, %g5 /* IEU0 Group */ - + andcc %g5, 0xff, %g0 /* IEU1 Group */ be,pn %icc, 20f /* CTI */ stb %g5, [%o0] /* Store */ @@ -236,7 +236,7 @@ ENTRY(strncpy) subcc %o2, 1, %o2 /* IEU1 */ be,pn %XCC, 19f /* CTI */ srlx %o3, 8, %g5 /* IEU0 Group */ - stb %g5, [%o0] /* Store */ + stb %g5, [%o0] /* Store */ 19: retl /* CTI+IEU1 Group */ mov %g6, %o0 /* IEU0 */ diff --git a/sysdeps/unix/bsd/times.c b/sysdeps/unix/bsd/times.c index f7aaea3..f0765bd 100644 --- a/sysdeps/unix/bsd/times.c +++ b/sysdeps/unix/bsd/times.c @@ -54,7 +54,7 @@ __times (buffer) } clk_tck = __getclktck (); - + if (__getrusage (RUSAGE_SELF, &usage) < 0) return (clock_t) -1; buffer->tms_utime = (clock_t) timeval_to_clock_t (&usage.ru_utime, clk_tck); diff --git a/sysdeps/unix/sysv/linux/a.out.h b/sysdeps/unix/sysv/linux/a.out.h index f0514c9..e3f4bdd 100644 --- a/sysdeps/unix/sysv/linux/a.out.h +++ b/sysdeps/unix/sysv/linux/a.out.h @@ -50,7 +50,7 @@ enum machine_type #define NMAGIC 0410 /* Code indicating demand-paged executable. */ #define ZMAGIC 0413 -/* This indicates a demand-paged executable with the header in the text. +/* This indicates a demand-paged executable with the header in the text. The first page is unmapped to help trap NULL pointer references. */ #define QMAGIC 0314 /* Code indicating core file. */ diff --git a/sysdeps/unix/sysv/linux/net/if_ppp.h b/sysdeps/unix/sysv/linux/net/if_ppp.h index bf5ec83..1b1c3ea 100644 --- a/sysdeps/unix/sysv/linux/net/if_ppp.h +++ b/sysdeps/unix/sysv/linux/net/if_ppp.h @@ -3,7 +3,7 @@ /* * if_ppp.h - Point-to-Point Protocol definitions. * - * Copyright (c) 1989 Carnegie Mellon University. + * Copyright (c) 1989 Carnegie Mellon University. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S index f1de10f..b97b993 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S @@ -51,8 +51,8 @@ versioned_symbol (libc, __setcontext, setcontext, GLIBC_2_3_4) #if SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4) compat_text_section - -# undef __CONTEXT_FUNC_NAME + +# undef __CONTEXT_FUNC_NAME # define __CONTEXT_FUNC_NAME __novec_setcontext # undef __CONTEXT_ENABLE_VRS diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S index 4dd9c0a..7ee4ef1 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S @@ -49,8 +49,8 @@ versioned_symbol (libc, __swapcontext, swapcontext, GLIBC_2_3_4) #if SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4) compat_text_section - -# undef __CONTEXT_FUNC_NAME + +# undef __CONTEXT_FUNC_NAME # define __CONTEXT_FUNC_NAME __novec_swapcontext # undef __CONTEXT_ENABLE_VRS diff --git a/sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions b/sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions index 3ff01d1..16d7128 100644 --- a/sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions +++ b/sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions @@ -12,11 +12,11 @@ libc { readdir64; readdir64_r; # s* - scandir64; + scandir64; } GLIBC_2.3.4 { getcontext; - setcontext; + setcontext; swapcontext; } GLIBC_2.17 { diff --git a/sysdeps/unix/sysv/linux/powerpc/sys/procfs.h b/sysdeps/unix/sysv/linux/powerpc/sys/procfs.h index 9f60b71..b046897 100644 --- a/sysdeps/unix/sysv/linux/powerpc/sys/procfs.h +++ b/sysdeps/unix/sysv/linux/powerpc/sys/procfs.h @@ -31,9 +31,9 @@ __BEGIN_DECLS -/* These definitions are normally provided by ucontext.h via - asm/sigcontext.h, asm/ptrace.h, and asm/elf.h. Otherwise we define - them here. */ +/* These definitions are normally provided by ucontext.h via + asm/sigcontext.h, asm/ptrace.h, and asm/elf.h. Otherwise we define + them here. */ #if !defined __PPC64_ELF_H && !defined _ASM_POWERPC_ELF_H #define ELF_NGREG 48 /* includes nip, msr, lr, etc. */ #define ELF_NFPREG 33 /* includes fpscr */ diff --git a/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h b/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h index 9358065..935a68c 100644 --- a/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h +++ b/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h @@ -61,14 +61,14 @@ typedef struct #else -/* For 64-bit kernels with Altivec support, a machine context is exactly - * a sigcontext. For older kernel (without Altivec) the sigcontext matches - * the mcontext upto but not including the v_regs field. For kernels that - * don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the +/* For 64-bit kernels with Altivec support, a machine context is exactly + * a sigcontext. For older kernel (without Altivec) the sigcontext matches + * the mcontext upto but not including the v_regs field. For kernels that + * don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the * v_regs field may not exit and should not be referenced. The v_regd field * can be refernced safely only after verifying that PPC_FEATURE_HAS_ALTIVEC * is set in AT_HWCAP. */ - + /* Number of general registers. */ # define NGREG 48 /* includes r0-r31, nip, msr, lr, etc. */ # define NFPREG 33 /* includes fp0-fp31 &fpscr. */ @@ -78,7 +78,7 @@ typedef unsigned long gregset_t[NGREG]; typedef double fpregset_t[NFPREG]; /* Container for Altivec/VMX Vector Status and Control Register. Only 32-bits - but can only be copied to/from a 128-bit vector register. So we allocated + but can only be copied to/from a 128-bit vector register. So we allocated a whole quadword speedup save/restore. */ typedef struct _libc_vscr { @@ -106,22 +106,22 @@ typedef struct { gregset_t gp_regs; fpregset_t fp_regs; /* - * To maintain compatibility with current implementations the sigcontext is - * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) - * followed by an unstructured (vmx_reserve) field of 69 doublewords. This - * allows the array of vector registers to be quadword aligned independent of - * the alignment of the containing sigcontext or ucontext. It is the - * responsibility of the code setting the sigcontext to set this pointer to - * either NULL (if this processor does not support the VMX feature) or the + * To maintain compatibility with current implementations the sigcontext is + * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) + * followed by an unstructured (vmx_reserve) field of 69 doublewords. This + * allows the array of vector registers to be quadword aligned independent of + * the alignment of the containing sigcontext or ucontext. It is the + * responsibility of the code setting the sigcontext to set this pointer to + * either NULL (if this processor does not support the VMX feature) or the * address of the first quadword within the allocated (vmx_reserve) area. * - * The pointer (v_regs) of vector type (elf_vrreg_t) is essentually - * an array of 34 quadword entries. The entries with - * indexes 0-31 contain the corresponding vector registers. The entry with - * index 32 contains the vscr as the last word (offset 12) within the - * quadword. This allows the vscr to be stored as either a quadword (since - * it must be copied via a vector register to/from storage) or as a word. - * The entry with index 33 contains the vrsave as the first word (offset 0) + * The pointer (v_regs) of vector type (elf_vrreg_t) is essentually + * an array of 34 quadword entries. The entries with + * indexes 0-31 contain the corresponding vector registers. The entry with + * index 32 contains the vscr as the last word (offset 12) within the + * quadword. This allows the vscr to be stored as either a quadword (since + * it must be copied via a vector register to/from storage) or as a word. + * The entry with index 33 contains the vrsave as the first word (offset 0) * within the quadword. */ vrregset_t *v_regs; diff --git a/sysdeps/unix/sysv/linux/s390/s390-32/clone.S b/sysdeps/unix/sysv/linux/s390/s390-32/clone.S index a3652a9..dc7835d 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-32/clone.S +++ b/sysdeps/unix/sysv/linux/s390/s390-32/clone.S @@ -52,7 +52,7 @@ error: lhi %r2,-EINVAL j SYSCALL_ERROR_LABEL PSEUDO_END (__clone) - + thread_start: #ifdef RESET_PID tmh %r3,1 /* CLONE_THREAD == 0x00010000 */ diff --git a/sysdeps/unix/sysv/linux/s390/s390-32/getcontext.S b/sysdeps/unix/sysv/linux/s390/s390-32/getcontext.S index 0a2e63e..6923f0e 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-32/getcontext.S +++ b/sysdeps/unix/sysv/linux/s390/s390-32/getcontext.S @@ -24,7 +24,7 @@ /* __getcontext (const ucontext_t *ucp) Saves the machine context in UCP such that when it is activated, - it appears as if __getcontext() returned again. + it appears as if __getcontext() returned again. This implementation is intended to be used for *synchronous* context switches only. Therefore, it does not have to save anything diff --git a/sysdeps/unix/sysv/linux/s390/s390-32/posix_fadvise64.c b/sysdeps/unix/sysv/linux/s390/s390-32/posix_fadvise64.c index f4b0dae..08032bd 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-32/posix_fadvise64.c +++ b/sysdeps/unix/sysv/linux/s390/s390-32/posix_fadvise64.c @@ -38,7 +38,7 @@ __posix_fadvise64_l64 (int fd, off64_t offset, off64_t len, int advise) { struct fadvise64_64_layout parameters; INTERNAL_SYSCALL_DECL (err); - + parameters.fd = fd; parameters.offset = offset; parameters.len = len; diff --git a/sysdeps/unix/sysv/linux/s390/s390-32/setcontext.S b/sysdeps/unix/sysv/linux/s390/s390-32/setcontext.S index ac25bea..03d2008 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-32/setcontext.S +++ b/sysdeps/unix/sysv/linux/s390/s390-32/setcontext.S @@ -58,7 +58,7 @@ ENTRY(__setcontext) ld %f13,SC_FPRS+104(%r1) ld %f14,SC_FPRS+112(%r1) ld %f15,SC_FPRS+120(%r1) - + /* Don't touch %a0, used for thread purposes. */ lam %a1,%a15,SC_ACRS+4(%r1) diff --git a/sysdeps/unix/sysv/linux/s390/s390-32/swapcontext.S b/sysdeps/unix/sysv/linux/s390/s390-32/swapcontext.S index ecb0b3f..b022f2c 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-32/swapcontext.S +++ b/sysdeps/unix/sysv/linux/s390/s390-32/swapcontext.S @@ -70,7 +70,7 @@ ENTRY(__swapcontext) /* Store general purpose registers. */ stm %r0,%r15,SC_GPRS(%r1) - + /* sigprocmask (SIG_SETMASK, &sc->sc_mask, NULL). */ la %r2,SIG_BLOCK lr %r5,%r0 @@ -98,7 +98,7 @@ ENTRY(__swapcontext) ld %f13,SC_FPRS+104(%r5) ld %f14,SC_FPRS+112(%r5) ld %f15,SC_FPRS+120(%r5) - + /* Don't touch %a0, used for thread purposes. */ lam %a1,%a15,SC_ACRS+4(%r5) @@ -107,5 +107,5 @@ ENTRY(__swapcontext) /* Return. */ br %r14 -END(__swapcontext) +END(__swapcontext) weak_alias (__swapcontext, swapcontext) diff --git a/sysdeps/unix/sysv/linux/s390/s390-64/mmap.S b/sysdeps/unix/sysv/linux/s390/s390-64/mmap.S index 379450c..2d2ef0c 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-64/mmap.S +++ b/sysdeps/unix/sysv/linux/s390/s390-64/mmap.S @@ -43,7 +43,7 @@ ENTRY(__mmap) stg %r1,0(%r15) /* Store back chain. */ stg %r0,8(%r15) /* Store eos. */ - /* Store parameters on stack, because old_mmap + /* Store parameters on stack, because old_mmap takes only one parameter: a pointer to the parameter area. */ mvc 200(8,%r15),368(%r15) /* Move 'offset'. */ lgfr %r6,%r6 @@ -63,7 +63,7 @@ ENTRY(__mmap) cfi_adjust_cfa_offset (-208) lmg %r6,%r15,48(%r15) /* Load registers. */ - /* Check gpr 2 for error. */ + /* Check gpr 2 for error. */ lghi %r0,-4096 clgr %r2,%r0 jgnl SYSCALL_ERROR_LABEL diff --git a/sysdeps/unix/sysv/linux/s390/s390-64/register-dump.h b/sysdeps/unix/sysv/linux/s390/s390-64/register-dump.h index d487897..3067c4c 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-64/register-dump.h +++ b/sysdeps/unix/sysv/linux/s390/s390-64/register-dump.h @@ -82,7 +82,7 @@ register_dump (int fd, struct sigcontext *ctx) hexvalue (ctx->sregs->regs.gprs[15], regs[15], 16); hexvalue (ctx->sregs->regs.psw.mask, regs[16], 16); hexvalue (ctx->sregs->regs.psw.addr, regs[17], 16); - + /* Generate the output. */ ADD_STRING ("Register dump:\n\n GPR0: "); ADD_MEM (regs[0], 16); diff --git a/sysdeps/unix/sysv/linux/s390/s390-64/setcontext.S b/sysdeps/unix/sysv/linux/s390/s390-64/setcontext.S index 8157327..f9ce7b6 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-64/setcontext.S +++ b/sysdeps/unix/sysv/linux/s390/s390-64/setcontext.S @@ -61,7 +61,7 @@ ENTRY(__setcontext) /* Don't touch %a0 and %a1, used for thread purposes. */ lam %a2,%a15,SC_ACRS+8(%r1) - + /* Load general purpose registers. */ lmg %r0,%r15,SC_GPRS(%r1) diff --git a/sysdeps/unix/sysv/linux/s390/s390-64/socket.S b/sysdeps/unix/sysv/linux/s390/s390-64/socket.S index 0887257..e3fb8b9 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-64/socket.S +++ b/sysdeps/unix/sysv/linux/s390/s390-64/socket.S @@ -100,10 +100,10 @@ ENTRY(__socket) lmg %r6,15,48(%r15) /* Load registers. */ /* gpr2 is < 0 if there was an error. */ - lghi %r0,-125 + lghi %r0,-125 clgr %r2,%r0 jgnl SYSCALL_ERROR_LABEL - + /* Successful; return the syscall's value. */ br %r14 diff --git a/sysdeps/unix/sysv/linux/s390/s390-64/swapcontext.S b/sysdeps/unix/sysv/linux/s390/s390-64/swapcontext.S index a08e68c..a626660 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-64/swapcontext.S +++ b/sysdeps/unix/sysv/linux/s390/s390-64/swapcontext.S @@ -101,11 +101,11 @@ ENTRY(__swapcontext) /* Don't touch %a0 and %a1, used for thread purposes. */ lam %a2,%a15,SC_ACRS+8(%r5) - + /* Load general purpose registers. */ lmg %r0,%r15,SC_GPRS(%r5) /* Return. */ br %r14 -END(__swapcontext) +END(__swapcontext) weak_alias (__swapcontext, swapcontext) diff --git a/sysdeps/unix/sysv/linux/s390/s390-64/syscall.S b/sysdeps/unix/sysv/linux/s390/s390-64/syscall.S index ab90eee..f204d25 100644 --- a/sysdeps/unix/sysv/linux/s390/s390-64/syscall.S +++ b/sysdeps/unix/sysv/linux/s390/s390-64/syscall.S @@ -40,7 +40,7 @@ ENTRY (syscall) cfi_adjust_cfa_offset (160) stg %r1,0(%r15) /* Store back chain. */ stg %r0,8(%r15) /* Store eos. */ - + lgr %r1,%r2 /* Move syscall number. */ lgr %r2,%r3 /* First parameter. */ lgr %r3,%r4 /* Second parameter. */ diff --git a/sysdeps/unix/sysv/linux/scsi/scsi_ioctl.h b/sysdeps/unix/sysv/linux/scsi/scsi_ioctl.h index 15ed314..d151580 100644 --- a/sysdeps/unix/sysv/linux/scsi/scsi_ioctl.h +++ b/sysdeps/unix/sysv/linux/scsi/scsi_ioctl.h @@ -16,7 +16,7 @@ <http://www.gnu.org/licenses/>. */ #ifndef _SCSI_IOCTL_H -#define _SCSI_IOCTL_H +#define _SCSI_IOCTL_H /* IOCTLs for SCSI. */ #define SCSI_IOCTL_SEND_COMMAND 1 /* Send a command to the SCSI host. */ diff --git a/sysdeps/unix/sysv/linux/sh/brk.c b/sysdeps/unix/sysv/linux/sh/brk.c index ae8a97b..d9097d3 100644 --- a/sysdeps/unix/sysv/linux/sh/brk.c +++ b/sysdeps/unix/sysv/linux/sh/brk.c @@ -31,7 +31,7 @@ __brk (void *addr) register long r4 asm ("%r4") = (long)addr; asm volatile ("trapa #0x11\n\t" SYSCALL_INST_PAD - : "=z"(newbrk) + : "=z"(newbrk) : "r" (r3), "r" (r4)); __curbrk = newbrk; diff --git a/sysdeps/unix/sysv/linux/sh/clone.S b/sysdeps/unix/sysv/linux/sh/clone.S index bcbe9e7..1a8fb4e 100644 --- a/sysdeps/unix/sysv/linux/sh/clone.S +++ b/sysdeps/unix/sysv/linux/sh/clone.S @@ -56,7 +56,7 @@ ENTRY(__clone) not r1, r1 // r1=0 means r0 = -1 to -4095 tst r1, r1 // i.e. error in linux bf .Lclone_end -.Lsyscall_error: +.Lsyscall_error: SYSCALL_ERROR_HANDLER .Lclone_end: tst r0, r0 @@ -84,10 +84,10 @@ ENTRY(__clone) stc gbr, r1 mov.w .Lpidoff, r2 add r1, r2 - mov.l r0, @r2 + mov.l r0, @r2 mov.w .Ltidoff, r2 add r1, r2 - mov.l r0, @r2 + mov.l r0, @r2 4: #endif /* thread starts */ diff --git a/sysdeps/unix/sysv/linux/sh/sh3/getcontext.S b/sysdeps/unix/sysv/linux/sh/sh3/getcontext.S index 263abb3..50b99fb 100644 --- a/sysdeps/unix/sysv/linux/sh/sh3/getcontext.S +++ b/sysdeps/unix/sysv/linux/sh/sh3/getcontext.S @@ -73,7 +73,7 @@ ENTRY(__getcontext) not r1, r1 // r1=0 means r0 = -1 to -4095 tst r1, r1 // i.e. error in linux bf .Lgetcontext_end -.Lsyscall_error: +.Lsyscall_error: SYSCALL_ERROR_HANDLER .Lgetcontext_end: /* All done, return 0 for success. */ diff --git a/sysdeps/unix/sysv/linux/sh/sh3/register-dump.h b/sysdeps/unix/sysv/linux/sh/sh3/register-dump.h index 6b2145f..5277b60 100644 --- a/sysdeps/unix/sysv/linux/sh/sh3/register-dump.h +++ b/sysdeps/unix/sysv/linux/sh/sh3/register-dump.h @@ -30,15 +30,15 @@ MACL: XXXXXXXX MACH: XXXXXXXX PC: XXXXXXXX PR: XXXXXXXX GBR: XXXXXXXX SR: XXXXXXXX - FR0: XXXXXXXX FR1: XXXXXXXX FR2: XXXXXXXX FR3: XXXXXXXX - FR4: XXXXXXXX FR5: XXXXXXXX FR6: XXXXXXXX FR7: XXXXXXXX - FR8: XXXXXXXX FR9: XXXXXXXX FR10: XXXXXXXX FR11: XXXXXXXX -FR12: XXXXXXXX FR13: XXXXXXXX FR14: XXXXXXXX FR15: XXXXXXXX - - XR0: XXXXXXXX XR1: XXXXXXXX XR2: XXXXXXXX XR3: XXXXXXXX - XR4: XXXXXXXX XR5: XXXXXXXX XR6: XXXXXXXX XR7: XXXXXXXX - XR8: XXXXXXXX XR9: XXXXXXXX XR10: XXXXXXXX XR11: XXXXXXXX -XR12: XXXXXXXX XR13: XXXXXXXX XR14: XXXXXXXX XR15: XXXXXXXX + FR0: XXXXXXXX FR1: XXXXXXXX FR2: XXXXXXXX FR3: XXXXXXXX + FR4: XXXXXXXX FR5: XXXXXXXX FR6: XXXXXXXX FR7: XXXXXXXX + FR8: XXXXXXXX FR9: XXXXXXXX FR10: XXXXXXXX FR11: XXXXXXXX +FR12: XXXXXXXX FR13: XXXXXXXX FR14: XXXXXXXX FR15: XXXXXXXX + + XR0: XXXXXXXX XR1: XXXXXXXX XR2: XXXXXXXX XR3: XXXXXXXX + XR4: XXXXXXXX XR5: XXXXXXXX XR6: XXXXXXXX XR7: XXXXXXXX + XR8: XXXXXXXX XR9: XXXXXXXX XR10: XXXXXXXX XR11: XXXXXXXX +XR12: XXXXXXXX XR13: XXXXXXXX XR14: XXXXXXXX XR15: XXXXXXXX FPSCR: XXXXXXXX FPUL: XXXXXXXX diff --git a/sysdeps/unix/sysv/linux/sh/sh3/setcontext.S b/sysdeps/unix/sysv/linux/sh/sh3/setcontext.S index cc5f34f..1bd8041 100644 --- a/sysdeps/unix/sysv/linux/sh/sh3/setcontext.S +++ b/sysdeps/unix/sysv/linux/sh/sh3/setcontext.S @@ -41,7 +41,7 @@ ENTRY(__setcontext) not r1, r1 // r1=0 means r0 = -1 to -4095 tst r1, r1 // i.e. error in linux bf .Lsetcontext_restore -.Lsyscall_error: +.Lsyscall_error: SYSCALL_ERROR_HANDLER .Lpseudo_end: rts diff --git a/sysdeps/unix/sysv/linux/sh/sh3/swapcontext.S b/sysdeps/unix/sysv/linux/sh/sh3/swapcontext.S index d4afa78..e42fd35 100644 --- a/sysdeps/unix/sysv/linux/sh/sh3/swapcontext.S +++ b/sysdeps/unix/sysv/linux/sh/sh3/swapcontext.S @@ -75,12 +75,12 @@ ENTRY(__swapcontext) not r1, r1 // r1=0 means r0 = -1 to -4095 tst r1, r1 // i.e. error in linux bf .Lswapcontext_restore -.Lsyscall_error: +.Lsyscall_error: SYSCALL_ERROR_HANDLER .Lpseudo_end: rts nop -.Lswapcontext_restore: +.Lswapcontext_restore: mov r8, r0 add #(oPC), r0 mov.l @r0+, r2 @@ -126,7 +126,7 @@ ENTRY(__swapcontext) cfi_adjust_cfa_offset(-4) jmp @r0 mov.l @r15+, r0 - + PSEUDO_END(__swapcontext) weak_alias (__swapcontext, swapcontext) diff --git a/sysdeps/unix/sysv/linux/sh/vfork.S b/sysdeps/unix/sysv/linux/sh/vfork.S index 6a1d827..8099fec 100644 --- a/sysdeps/unix/sysv/linux/sh/vfork.S +++ b/sysdeps/unix/sysv/linux/sh/vfork.S @@ -58,7 +58,7 @@ ENTRY (__vfork) not r1, r1 // r1=0 means r0 = -1 to -4095 tst r1, r1 // i.e. error in linux bf .Lpseudo_end -.Lsyscall_error: +.Lsyscall_error: SYSCALL_ERROR_HANDLER .Lpseudo_end: rts diff --git a/sysdeps/unix/sysv/linux/sparc/a.out.h b/sysdeps/unix/sysv/linux/sparc/a.out.h index 6ea7065..593c4cc 100644 --- a/sysdeps/unix/sysv/linux/sparc/a.out.h +++ b/sysdeps/unix/sysv/linux/sparc/a.out.h @@ -53,7 +53,7 @@ enum machine_type #define NMAGIC 0410 /* Code indicating demand-paged executable. */ #define ZMAGIC 0413 -/* This indicates a demand-paged executable with the header in the text. +/* This indicates a demand-paged executable with the header in the text. The first page is unmapped to help trap NULL pointer references. */ #define QMAGIC 0314 /* Code indicating core file. */ diff --git a/sysdeps/unix/sysv/linux/sparc/sparc64/brk.S b/sysdeps/unix/sysv/linux/sparc/sparc64/brk.S index 7276d73..e9b9808 100644 --- a/sysdeps/unix/sysv/linux/sparc/sparc64/brk.S +++ b/sysdeps/unix/sysv/linux/sparc/sparc64/brk.S @@ -74,7 +74,7 @@ ENTRY (__brk) /* Don't use "ret" cause the preprocessor will eat it. */ jmpl %i7+8, %g0 restore - + /* What a horrible way to die. */ .Lerr0: set ENOMEM, %o0 .Lerr1: diff --git a/sysdeps/unix/sysv/linux/sys/personality.h b/sysdeps/unix/sysv/linux/sys/personality.h index f2abac2..bab1217 100644 --- a/sysdeps/unix/sysv/linux/sys/personality.h +++ b/sysdeps/unix/sysv/linux/sys/personality.h @@ -41,7 +41,7 @@ enum These go in the low byte. Avoid using the top bit, it will conflict with error returns. */ -enum +enum { PER_LINUX = 0x0000, PER_LINUX_32BIT = 0x0000 | ADDR_LIMIT_32BIT, diff --git a/sysdeps/x86_64/fpu/s_ceill.S b/sysdeps/x86_64/fpu/s_ceill.S index efc8dd9..910c371 100644 --- a/sysdeps/x86_64/fpu/s_ceill.S +++ b/sysdeps/x86_64/fpu/s_ceill.S @@ -1,7 +1,7 @@ /* * Written by J.T. Conklin <jtc@netbsd.org>. * Changes for long double by Ulrich Drepper <drepper@cygnus.com> - * Changes for x86-64 by Andreas Jaeger <aj@suse.de> + * Changes for x86-64 by Andreas Jaeger <aj@suse.de> * Public domain. */ diff --git a/sysdeps/x86_64/fpu/s_llrintl.S b/sysdeps/x86_64/fpu/s_llrintl.S index ea9c2f3..8c6f72e 100644 --- a/sysdeps/x86_64/fpu/s_llrintl.S +++ b/sysdeps/x86_64/fpu/s_llrintl.S @@ -30,4 +30,4 @@ END(__llrintl) weak_alias (__llrintl, llrintl) strong_alias (__llrintl, __lrintl) weak_alias (__llrintl, lrintl) - + diff --git a/sysdeps/x86_64/strcspn.S b/sysdeps/x86_64/strcspn.S index ff9fa53..65f8a9e 100644 --- a/sysdeps/x86_64/strcspn.S +++ b/sysdeps/x86_64/strcspn.S @@ -115,7 +115,7 @@ L(4): addq $256, %rsp /* remove skipset */ xorl %edx,%edx orb %cl, %cl /* was last character NUL? */ cmovzq %rdx, %rax /* Yes: return NULL */ -#else +#else subq %rdx, %rax /* we have to return the number of valid characters, so compute distance to first non-valid character */ |