aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAurelien Jarno <aurelien@aurel32.net>2022-10-03 23:46:11 +0200
committerAurelien Jarno <aurelien@aurel32.net>2022-10-03 23:46:11 +0200
commitb80f16adbd979831bf25ea491e1261e81885c2b6 (patch)
tree9c1db7bfabd794f0c84ad4896c68ef33673f1620
parent653c12c7d880340462bd963752619a7a61bcb4e3 (diff)
downloadglibc-b80f16adbd979831bf25ea491e1261e81885c2b6.zip
glibc-b80f16adbd979831bf25ea491e1261e81885c2b6.tar.gz
glibc-b80f16adbd979831bf25ea491e1261e81885c2b6.tar.bz2
x86: include BMI1 and BMI2 in x86-64-v3 level
The "System V Application Binary Interface AMD64 Architecture Processor Supplement" mandates the BMI1 and BMI2 CPU features for the x86-64-v3 level. Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
-rw-r--r--sysdeps/x86/get-isa-level.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/sysdeps/x86/get-isa-level.h b/sysdeps/x86/get-isa-level.h
index 1ade78a..5b4dd5f 100644
--- a/sysdeps/x86/get-isa-level.h
+++ b/sysdeps/x86/get-isa-level.h
@@ -47,6 +47,8 @@ get_isa_level (const struct cpu_features *cpu_features)
isa_level |= GNU_PROPERTY_X86_ISA_1_V2;
if (CPU_FEATURE_USABLE_P (cpu_features, AVX)
&& CPU_FEATURE_USABLE_P (cpu_features, AVX2)
+ && CPU_FEATURE_USABLE_P (cpu_features, BMI1)
+ && CPU_FEATURE_USABLE_P (cpu_features, BMI2)
&& CPU_FEATURE_USABLE_P (cpu_features, F16C)
&& CPU_FEATURE_USABLE_P (cpu_features, FMA)
&& CPU_FEATURE_USABLE_P (cpu_features, LZCNT)