aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorRical Jasan <ricaljasan@pacific.net>2018-02-16 08:21:47 -0800
committerRical Jasan <ricaljasan@pacific.net>2018-02-16 08:21:47 -0800
commit16efad5171ac1ac2c8728405f2703045f08c494b (patch)
treedcdddab65c99830b0948de5d675c915fdeabe1de
parent8724507385a591a71297c2da0e12001eae6bd88d (diff)
downloadglibc-16efad5171ac1ac2c8728405f2703045f08c494b.zip
glibc-16efad5171ac1ac2c8728405f2703045f08c494b.tar.gz
glibc-16efad5171ac1ac2c8728405f2703045f08c494b.tar.bz2
manual: Fix a syntax error.
The opening parenthesis for function arguments in an @deftypefun need to be separated from the function name. This isn't just a matter of the GNU coding style---it causes the "(void" (in this case) to be rendered as a part of the function name, causing a visual defect, and also results in a warning to the following effect during `make pdf': Warning: unbalanced parentheses in @def...) * manual/platform.texi (__riscv_flush_icache): Fix @deftypefun syntax.
-rw-r--r--ChangeLog5
-rw-r--r--manual/platform.texi2
2 files changed, 6 insertions, 1 deletions
diff --git a/ChangeLog b/ChangeLog
index 50ba118..ee90bea 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2018-02-16 Rical Jasan <ricaljasan@pacific.net>
+
+ * manual/platform.texi (__riscv_flush_icache): Fix @deftypefun
+ syntax.
+
2018-02-16 Stefan Liebler <stli@linux.vnet.ibm.com>
* nptl/Makefile (tst-mutex8-ENV): Delete.
diff --git a/manual/platform.texi b/manual/platform.texi
index b8721a0..504addc 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -123,7 +123,7 @@ when it is not allowed, the priority is set to medium.
Cache management facilities specific to RISC-V systems that implement the Linux
ABI are declared in @file{sys/cachectl.h}.
-@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags})
+@deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags})
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Enforce ordering between stores and instruction cache fetches. The range of
addresses over which ordering is enforced is specified by @var{start} and