1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
|
# Hitachi H8 testcase 'and.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# and.b #xx:8, rd ; e rd xxxxxxxx
# and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx
# and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
# and.b rs, rd ; 1 6 rs rd
# and.b reg8, @erd ; 7 d rd ???? 1 6 rs ????
# and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs
# and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs
# and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs
# and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs
#
# andc #xx:8, ccr ; 0 6 xxxxxxxx
# andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
and_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.b #xx:8,Rd
and.b #0xaa, r0l ; Immediate 8-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a0 r0 ; and result: a5 & aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
and_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd
mov #byte_dest, er0
and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L1
fail
.L1:
and_b_imm8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd+
mov #byte_dest, er0
and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xe055
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L2
fail
.L2:
;; special case same register
mov.l #byte_dest, er0
mov.b @er0, r1h
mov.b r0l, r1l
and.b r0l, @er0+
inc.b r1l
and.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L22
fail
.L22:
and_b_imm8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd-
mov #byte_dest, er0
and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L3
fail
.L3:
;; special case same register
mov.l #byte_dest, er0
mov.b @er0, r1h
mov.b r0l, r1l
and.b r0l, @er0-
dec.b r1l
and.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L23
fail
.L23:
and_b_imm8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@+eRd
mov #pre_byte, er0
and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xe055
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L4
fail
.L4:
;; special case same register
mov.l #pre_byte, er0
mov.b @byte_dest, r1h
mov.b r0l, r1l
and.b r0l, @+er0
inc.b r1l
and.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L24
fail
.L24:
and_b_imm8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@-eRd
mov #post_byte, er0
and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L5
fail
.L5:
;; special case same register
mov.l #post_byte, er0
mov.b @byte_dest, r1h
mov.b r0l, r1l
and.b r0l, @-er0
dec.b r1l
and.b r1h, r1l
mov.b @byte_dest, r0l
cmp.b r1l, r0l
beq .L25
fail
.L25:
.endif ; h8sx
and_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.b Rs,Rd
mov.b #0xaa, r0h
and.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xaaa0 r0 ; and result: a5 & aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
and_b_reg8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd ; And to register indirect
mov #byte_dest, er0
mov #0x55, r1l
and.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1690
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L6
fail
.L6:
and_b_reg8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd+ ; And to register post-incr
mov #byte_dest, er0
mov #0xaa, r1l
and.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8069
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L7
fail
.L7:
and_b_reg8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd- ; And to register post-decr
mov #byte_dest, er0
mov #0x55, r1l
and.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa069
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L8
fail
.L8:
and_b_reg8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@+eRd ; And to register post-incr
mov #pre_byte, er0
mov #0xaa, r1l
and.b r1l, @+er0 ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x9069
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L9
fail
.L9:
and_b_reg8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@-eRd ; And to register post-decr
mov #post_byte, er0
mov #0x55, r1l
and.b r1l, @-er0 ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xb069
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L10
fail
.L10:
.endif ; h8sx
andc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; andc #xx:8,ccr
set_ccr 0xff
test_neg_set
andc #0xf7, ccr ; Immediate 8-bit operand (neg flag)
test_neg_clear
test_zero_set
andc #0xfb, ccr ; Immediate 8-bit operand (zero flag)
test_zero_clear
test_ovf_set
andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_clear
test_carry_set
andc #0xfe, ccr ; Immediate 8-bit operand (carry flag)
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
andc_imm8_exr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
ldc #0xff, exr
stc exr, r0l
test_h_gr8 0x87, r0l
;; andc #xx:8,exr
set_ccr_zero
andc #0x7f, exr
test_cc_clear
stc exr, r0l
test_h_gr8 0x7, r0l
andc #0x3, exr
stc exr, r0l
test_h_gr8 0x3, r0l
andc #0x1, exr
stc exr, r0l
test_h_gr8 0x1, r0l
andc #0x0, exr
stc exr, r0l
test_h_gr8 0x0, r0l
test_h_gr32 0xa5a5a500 er0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif ; not h8300 or h8300h
pass
exit 0
|
