1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
# frv testcase for nfadds $GRi,$GRj,$GRk
# mach: fr500 fr550 frv
.include "testutils.inc"
float_constants
start
load_float_constants
.global nfadds
nfadds:
nfadds fr16,fr0,fr1
test_fr_fr fr1,fr0
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr4,fr1
test_fr_fr fr1,fr4
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr8,fr1
test_fr_fr fr1,fr8
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr12,fr1
test_fr_fr fr1,fr12
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr16,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr20,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr24,fr1
test_fr_fr fr1,fr24
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr28,fr1
test_fr_fr fr1,fr28
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr32,fr1
test_fr_fr fr1,fr32
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr36,fr1
test_fr_fr fr1,fr36
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr40,fr1
test_fr_fr fr1,fr40
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr44,fr1
test_fr_fr fr1,fr44
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr48,fr1
test_fr_fr fr1,fr48
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr16,fr52,fr1
test_fr_fr fr1,fr52
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr0,fr1
test_fr_fr fr1,fr0
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr4,fr1
test_fr_fr fr1,fr4
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr8,fr1
test_fr_fr fr1,fr8
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr12,fr1
test_fr_fr fr1,fr12
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr16,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr20,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr24,fr1
test_fr_fr fr1,fr24
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr28,fr1
test_fr_fr fr1,fr28
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr32,fr1
test_fr_fr fr1,fr32
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr36,fr1
test_fr_fr fr1,fr36
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr40,fr1
test_fr_fr fr1,fr40
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr44,fr1
test_fr_fr fr1,fr44
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr48,fr1
test_fr_fr fr1,fr48
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr20,fr52,fr1
test_fr_fr fr1,fr52
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr8,fr28,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr12,fr24,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr24,fr12,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr28,fr8,fr1
test_fr_fr fr1,fr16
test_fr_fr fr1,fr20
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr36,fr40,fr1
test_fr_fr fr1,fr44
test_spr_immed 0,fner1
test_spr_immed 0,fner0
; try to cause exceptions
nfadds fr48,fr28,fr1
; test_fr_fr fr1,fr44
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr52,fr28,fr1
; test_fr_fr fr1,fr44
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr56,fr28,fr1
; test_fr_fr fr1,fr44
test_spr_immed 0,fner1
test_spr_immed 0,fner0
nfadds fr60,fr28,fr1
; test_fr_fr fr1,fr44
test_spr_immed 2,fner1
test_spr_immed 0,fner0
pass
|