blob: b08a571a35605700e1d013005a4356302578e2a1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
# frv testcase for ftino
# mach: all
.include "testutils.inc"
start
.global ftinev
ftinev:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr7
inc_gr_immed 2112,gr7 ; address of exception handler
set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_gr_immed 0,gr7
set_fcc 0x0 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x1 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x2 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x3 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x4 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x5 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x6 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x7 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x8 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0x9 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0xa 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0xb 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0xc 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0xd 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0xe 0
ftino ; should branch to tbr + (128 + 4)*16
set_fcc 0xf 0
ftino ; should branch to tbr + (128 + 4)*16
pass
bad:
fail
|