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# frv testcase for bcclr $ICCi,$ccond,$hint
# mach: all
.include "testutils.inc"
start
.global bcclr
bcclr:
; ccond is true
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,0,0
set_spr_addr ok2,lr
set_icc 0x1 1
bcclr icc1,0,1
fail
ok2:
set_spr_addr bad,lr
set_icc 0x2 2
bcclr icc2,0,2
set_spr_addr ok4,lr
set_icc 0x3 3
bcclr icc3,0,3
fail
ok4:
set_spr_addr bad,lr
set_icc 0x4 0
bcclr icc0,0,0
set_spr_addr ok6,lr
set_icc 0x5 1
bcclr icc1,0,1
fail
ok6:
set_spr_addr bad,lr
set_icc 0x6 2
bcclr icc2,0,2
set_spr_addr ok8,lr
set_icc 0x7 3
bcclr icc3,0,3
fail
ok8:
set_spr_addr bad,lr
set_icc 0x8 0
bcclr icc0,0,0
set_spr_addr oka,lr
set_icc 0x9 1
bcclr icc1,0,1
fail
oka:
set_spr_addr bad,lr
set_icc 0xa 2
bcclr icc2,0,2
set_spr_addr okc,lr
set_icc 0xb 3
bcclr icc3,0,3
fail
okc:
set_spr_addr bad,lr
set_icc 0xc 0
bcclr icc0,0,0
set_spr_addr oke,lr
set_icc 0xd 1
bcclr icc1,0,1
fail
oke:
set_spr_addr bad,lr
set_icc 0xe 2
bcclr icc2,0,2
set_spr_addr okg,lr
set_icc 0xf 3
bcclr icc3,0,3
fail
okg:
; ccond is true
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr oki,lr
set_icc 0x1 1
bcclr icc1,1,1
fail
oki:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x2 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr okk,lr
set_icc 0x3 3
bcclr icc3,1,3
fail
okk:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x4 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr okm,lr
set_icc 0x5 1
bcclr icc1,1,1
fail
okm:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x6 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr oko,lr
set_icc 0x7 3
bcclr icc3,1,3
fail
oko:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x8 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr okq,lr
set_icc 0x9 1
bcclr icc1,1,1
fail
okq:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xa 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr oks,lr
set_icc 0xb 3
bcclr icc3,1,3
fail
oks:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xc 0
bcclr icc0,1,0
set_spr_immed 1,lcr
set_spr_addr oku,lr
set_icc 0xd 1
bcclr icc1,1,1
fail
oku:
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0xe 2
bcclr icc2,1,2
set_spr_immed 1,lcr
set_spr_addr okw,lr
set_icc 0xf 3
bcclr icc3,1,3
fail
okw:
; ccond is false
set_spr_immed 128,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,1,0
set_icc 0x1 1
bcclr icc1,1,1
set_icc 0x2 2
bcclr icc2,1,2
set_icc 0x3 3
bcclr icc3,1,3
set_icc 0x4 0
bcclr icc0,1,0
set_icc 0x5 1
bcclr icc1,1,1
set_icc 0x6 2
bcclr icc2,1,2
set_icc 0x7 3
bcclr icc3,1,3
set_icc 0x8 0
bcclr icc0,1,0
set_icc 0x9 1
bcclr icc1,1,1
set_icc 0xa 2
bcclr icc2,1,2
set_icc 0xb 3
bcclr icc3,1,3
set_icc 0xc 0
bcclr icc0,1,0
set_icc 0xd 1
bcclr icc1,1,1
set_icc 0xe 2
bcclr icc2,1,2
set_icc 0xf 3
bcclr icc3,1,3
; ccond is false
set_spr_immed 1,lcr
set_spr_addr bad,lr
set_icc 0x0 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x1 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x2 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x3 3
bcclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x4 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x5 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0x6 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0x7 3
bcclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0x8 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0x9 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xa 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xb 3
bcclr icc3,0,3
set_spr_immed 1,lcr
set_icc 0xc 0
bcclr icc0,0,0
set_spr_immed 1,lcr
set_icc 0xd 1
bcclr icc1,0,1
set_spr_immed 1,lcr
set_icc 0xe 2
bcclr icc2,0,2
set_spr_immed 1,lcr
set_icc 0xf 3
bcclr icc3,0,3
pass
bad:
fail
|
