1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
|
2003-09-03 Michael Snyder <msnyder@redhat.com>
* sim/frv/interrupts/Ipipe-fr400.cgs: New file.
* sim/frv/interrupts/Ipipe-fr500.cgs: New file.
* sim/frv/interrupts/Ipipe.cgs: Remove (replaced by above).
2003-08-20 Michael Snyder <msnyder@redhat.com>
On behalf of Dave Brolley
* sim/frv: New testsuite.
* frv-elf: New testsuite.
2003-07-09 Michael Snyder <msnyder@redhat.com>
* sim/sh: New directory. Tests for Renesas sh family.
2003-04-13 Michael Snyder <msnyder@redhat.com>
* sim/h8300: New directory. Tests for Renesas h8/300 family.
2003-04-01 Nick Clifton <nickc@redhat.com>
* sim/arm: New directory: Tests for ARM simulator.
* sim/arm/allinsn.exp: New file: Test script.
* sim/arm/testutils.inc: New file: Test macros.
* sim/arm/adc.cgs, sim/arm/add.cgs, sim/arm/and.cgs,
sim/arm/b.cgs, sim/arm/bic.cgs, sim/arm/bl.cgs, sim/arm/bx.cgs,
sim/arm/cmn.cgs, sim/arm/cmp.cgs, sim/arm/eor.cgs,
sim/arm/hello.ms, sim/arm/ldm.cgs, sim/arm/ldr.cgs,
sim/arm/ldrb.cgs, sim/arm/ldrh.cgs, sim/arm/ldrsb.cgs,
sim/arm/ldrsh.cgs, sim/arm/misaligned1.ms, sim/arm/misaligned2.ms,
sim/arm/misaligned3.ms, sim/arm/misc.exp, sim/arm/mla.cgs,
sim/arm/mov.cgs, sim/arm/mrs.cgs, sim/arm/msr.cgs,
sim/arm/mul.cgs, sim/arm/mvn.cgs, sim/arm/orr.cgs,
sim/arm/rsb.cgs, sim/arm/rsc.cgs, sim/arm/sbc.cgs,
sim/arm/smlal.cgs, sim/arm/smull.cgs, sim/arm/stm.cgs,
sim/arm/str.cgs, sim/arm/strb.cgs, sim/arm/strh.cgs,
sim/arm/sub.cgs, sim/arm/swi.cgs, sim/arm/swp.cgs,
sim/arm/swpb.cgs, sim/arm/teq.cgs, sim/arm/tst.cgs,
sim/arm/umlal.cgs, sim/arm/umull.cgs: New files: ARM tests.
* sim/arm/iwmmxt: New Directory: Tests for iWMMXt.
* sim/arm/iwmmxt/iwmmxt.exp: New file: Test script.
* sim/arm/iwmmxt/testutils.inc: New file: Test macros.
* sim/arm/iwmmxt/tbcst.cgs, sim/arm/iwmmxt/textrm.cgs,
sim/arm/iwmmxt/tinsr.cgs, sim/arm/iwmmxt/tmia.cgs,
sim/arm/iwmmxt/tmiaph.cgs, sim/arm/iwmmxt/tmiaxy.cgs,
sim/arm/iwmmxt/tmovmsk.cgss, sim/arm/iwmmxt/wacc.cgs,
sim/arm/iwmmxt/wadd.cgs, sim/arm/iwmmxt/waligni.cgs,
sim/arm/iwmmxt/walignr.cgs, sim/arm/iwmmxt/wand.cgs,
sim/arm/iwmmxt/wandn.cgs, sim/arm/iwmmxt/wavg2.cgs,
sim/arm/iwmmxt/wcmpeq.cgs, sim/arm/iwmmxt/wcmpgt.cgs,
sim/arm/iwmmxt/wmac.cgs, sim/arm/iwmmxt/wmadd.cgs,
sim/arm/iwmmxt/wmax.cgs, sim/arm/iwmmxt/wmin.cgs,
sim/arm/iwmmxt/wmov.cgs, sim/arm/iwmmxt/wmul.cgs,
sim/arm/iwmmxt/wor.cgs, sim/arm/iwmmxt/wpack.cgs,
sim/arm/iwmmxt/wror.cgs, sim/arm/iwmmxt/wsad.cgs,
sim/arm/iwmmxt/wshufh.cgs, sim/arm/iwmmxt/wsll.cgs,
sim/arm/iwmmxt/wsra.cgs, sim/arm/iwmmxt/wsrl.cgs,
sim/arm/iwmmxt/wsub.cgs, sim/arm/iwmmxt/wunpckeh.cgs,
sim/arm/iwmmxt/wunpckel.cgs, sim/arm/iwmmxt/wunpckih.cgs,
sim/arm/iwmmxt/wunpckil.cgs, sim/arm/iwmmxt/wxor.cgs,
sim/arm/iwmmxt/wzero.cgs: New files: iWMMXt tests.
* sim/arm/thumb: New Directory: Thumb tests.
* sim/arm/thumb/allthumb.exp: New file: Test script.
* sim/arm/thumb/testutils.inc: New file: Test macros.
* sim/arm/thumb/adc.cgs, sim/arm/thumb/add-hd-hs.cgs,
sim/arm/thumb/add-hd-rs.cgs, sim/arm/thumb/add-rd-hs.cgs,
sim/arm/thumb/add-sp.cgs, sim/arm/thumb/add.cgs,
sim/arm/thumb/addi.cgs, sim/arm/thumb/addi8.cgs,
sim/arm/thumb/and.cgs, sim/arm/thumb/asr.cgs, sim/arm/thumb/b.cgs,
sim/arm/thumb/bcc.cgs, sim/arm/thumb/bcs.cgs,
sim/arm/thumb/beq.cgs, sim/arm/thumb/bge.cgs,
sim/arm/thumb/bgt.cgs, sim/arm/thumb/bhi.cgs,
sim/arm/thumb/bic.cgs, sim/arm/thumb/bl-hi.cgs,
sim/arm/thumb/bl-lo.cgs, sim/arm/thumb/ble.cgs,
sim/arm/thumb/bls.cgs, sim/arm/thumb/blt.cgs,
sim/arm/thumb/bmi.cgs, sim/arm/thumb/bne.cgs,
sim/arm/thumb/bpl.cgs, sim/arm/thumb/bvc.cgs,
sim/arm/thumb/bvs.cgs, sim/arm/thumb/bx-hs.cgs,
sim/arm/thumb/bx-rs.cgs, sim/arm/thumb/cmn.cgs,
sim/arm/thumb/cmp-hd-hs.cgs, sim/arm/thumb/cmp-hd-rs.cgs,
sim/arm/thumb/cmp-rd-hs.cgs, sim/arm/thumb/cmp.cgs,
sim/arm/thumb/eor.cgs, sim/arm/thumb/lda-pc.cgs,
sim/arm/thumb/lda-sp.cgs, sim/arm/thumb/ldmia.cgs,
sim/arm/thumb/ldr-imm.cgs, sim/arm/thumb/ldr-pc.cgs,
sim/arm/thumb/ldr-sprel.cgs, sim/arm/thumb/ldr.cgs,
sim/arm/thumb/ldrb-imm.cgs, sim/arm/thumb/ldrb.cgs,
sim/arm/thumb/ldrh-imm.cgs, sim/arm/thumb/ldrh.cgs,
sim/arm/thumb/ldsb.cgs, sim/arm/thumb/ldsh.cgs,
sim/arm/thumb/lsl.cgs, sim/arm/thumb/lsr.cgs,
sim/arm/thumb/mov-hd-hs.cgs, sim/arm/thumb/mov-hd-rs.cgs,
sim/arm/thumb/mov-rd-hs.cgs, sim/arm/thumb/mov.cgs,
sim/arm/thumb/mul.cgs, sim/arm/thumb/mvn.cgs,
sim/arm/thumb/neg.cgs, sim/arm/thumb/orr.cgs,
sim/arm/thumb/pop-pc.cgs, sim/arm/thumb/pop.cgs,
sim/arm/thumb/push-lr.cgs, sim/arm/thumb/push.cgs,
sim/arm/thumb/ror.cgs, sim/arm/thumb/sbc.cgs,
sim/arm/thumb/stmia.cgs, sim/arm/thumb/str-imm.cgs,
sim/arm/thumb/str-sprel.cgs, sim/arm/thumb/str.cgs,
sim/arm/thumb/strb-imm.cgs, sim/arm/thumb/strb.cgs,
sim/arm/thumb/strh-imm.cgs, sim/arm/thumb/strh.cgs,
sim/arm/thumb/sub-sp.cgs, sim/arm/thumb/sub.cgs,
sim/arm/thumb/subi.cgs, sim/arm/thumb/subi8.cgs,
sim/arm/thumb/swi.cgs, sim/arm/thumb/tst.cgs: New files: Thumb
tests.
* sim/arm/xscale: New directory.
* sim/arm/xscale/xscale.exp: New file: Test script.
* sim/arm/xscale/testutils.inc: New file: Test macros.
* sim/arm/xscale/blx.cgs, sim/arm/xscale/mia.cgs,
sim/arm/xscale/miaph.cgs, sim/arm/xscale/miaxy.cgs,
sim/arm/xscale/mra.cgs: New files: XScale tests.
2002-06-16 Andrew Cagney <ac131313@redhat.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
2001-07-31 Ben Elliston <bje@redhat.com>
* lib/sim-defs.exp (run_sim_test): Include a description such as
"assembling" or "linking" that identifies the phase a test fails
in, for easier analysis of failures.
2000-11-01 Dave Brolley <brolley@cygnus.com>
* lib/sim-defs.exp (run_sm_test): Correct comment. "output" and
"xerror" options do not use a list of machines. Clear options from
previous test case. Use "$cpu_option" to identify the machine to the
assembler, if specified.
Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
1999-09-15 Doug Evans <devans@casey.cygnus.com>
* sim/arm/b.cgs: New testcase.
* sim/arm/bic.cgs: New testcase.
* sim/arm/bl.cgs: New testcase.
Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
1999-08-30 Doug Evans <devans@casey.cygnus.com>
* lib/sim-defs.exp (run_sim_test): Rename all_machs arg to
requested_machs, now is list of machs to run tests for.
Delete locals AS,ASFLAGS,LD,LDFLAGS. Use target_assemble
and target_link instead.
1999-04-21 Doug Evans <devans@casey.cygnus.com>
* sim/m32r/nop.cgs: Add missing nop insn.
Mon Mar 22 13:28:56 1999 Dave Brolley <brolley@cygnus.com>
* sim/fr30/stb.cgs: Correct for unaligned access.
* sim/fr30/sth.cgs: Correct for unaligned access.
* sim/fr30/ldub.cgs: Fix typo: lduh->ldub. Correct
for unaligned access.
* sim/fr30/and.cgs: Test unaligned access.
Fri Feb 5 12:41:11 1999 Doug Evans <devans@canuck.cygnus.com>
* lib/sim-defs.exp (sim_run): Print simulator arguments log message.
1999-01-05 Doug Evans <devans@casey.cygnus.com>
* lib/sim-defs.exp (run_sim_test): New arg all_machs.
* sim/fr30/allinsn.exp: Update.
* sim/fr30/misc.exp: Update.
* sim/m32r/allinsn.exp: Update.
* sim/m32r/misc.exp: Update.
Fri Dec 18 17:19:34 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/ldres.cgs: New testcase.
* sim/fr30/copld.cgs: New testcase.
* sim/fr30/copst.cgs: New testcase.
* sim/fr30/copsv.cgs: New testcase.
* sim/fr30/nop.cgs: New testcase.
* sim/fr30/andccr.cgs: New testcase.
* sim/fr30/orccr.cgs: New testcase.
* sim/fr30/addsp.cgs: New testcase.
* sim/fr30/stilm.cgs: New testcase.
* sim/fr30/extsb.cgs: New testcase.
* sim/fr30/extub.cgs: New testcase.
* sim/fr30/extsh.cgs: New testcase.
* sim/fr30/extuh.cgs: New testcase.
* sim/fr30/enter.cgs: New testcase.
* sim/fr30/leave.cgs: New testcase.
* sim/fr30/xchb.cgs: New testcase.
* sim/fr30/dmovb.cgs: New testcase.
* sim/fr30/dmov.cgs: New testcase.
* sim/fr30/dmovh.cgs: New testcase.
Thu Dec 17 17:18:43 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros.
* sim/fr30/ret.cgs: Add tests fir ret:d.
* sim/fr30/inte.cgs: New testcase.
* sim/fr30/reti.cgs: New testcase.
* sim/fr30/bra.cgs: New testcase.
* sim/fr30/bno.cgs: New testcase.
* sim/fr30/beq.cgs: New testcase.
* sim/fr30/bne.cgs: New testcase.
* sim/fr30/bc.cgs: New testcase.
* sim/fr30/bnc.cgs: New testcase.
* sim/fr30/bn.cgs: New testcase.
* sim/fr30/bp.cgs: New testcase.
* sim/fr30/bv.cgs: New testcase.
* sim/fr30/bnv.cgs: New testcase.
* sim/fr30/blt.cgs: New testcase.
* sim/fr30/bge.cgs: New testcase.
* sim/fr30/ble.cgs: New testcase.
* sim/fr30/bgt.cgs: New testcase.
* sim/fr30/bls.cgs: New testcase.
* sim/fr30/bhi.cgs: New testcase.
Tue Dec 15 17:47:13 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/div.cgs (int): Add signed division scenario.
* sim/fr30/int.cgs (int): Complete testcase.
* sim/fr30/testutils.inc (_start): Initialize tbr.
(test_s_user,test_s_system,set_i,test_i): New macros.
1998-12-14 Doug Evans <devans@casey.cygnus.com>
* lib/sim-defs.exp (run_sim_test): New option xerror, for expected
errors. Translate \n sequences in expected output to newline char.
(slurp_options): Make parentheses optional.
(sim_run): Look for board_info sim,options.
* sim/fr30/hello.ms: Add trailing \n to expected output.
* sim/m32r/hello.ms: Ditto.
* sim/m32r/hw-trap.ms: Ditto.
* sim/m32r/trap.cgs: Properly align trap2_handler.
* sim/m32r/uread16.ms: New testcase.
* sim/m32r/uread32.ms: New testcase.
* sim/m32r/uwrite16.ms: New testcase.
* sim/m32r/uwrite32.ms: New testcase.
1998-12-14 Dave Brolley <brolley@cygnus.com>
* sim/fr30/call.cgs: Test ret here as well.
* sim/fr30/ld.cgs: Remove bogus comment.
* sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
* sim/fr30/div.ms: New testcase.
* sim/fr30/st.cgs: New testcase.
* sim/fr30/sth.cgs: New testcase.
* sim/fr30/stb.cgs: New testcase.
* sim/fr30/mov.cgs: New testcase.
* sim/fr30/jmp.cgs: New testcase.
* sim/fr30/ret.cgs: New testcase.
* sim/fr30/int.cgs: New testcase.
Thu Dec 10 18:46:25 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/div0s.cgs: New testcase.
* sim/fr30/div0u.cgs: New testcase.
* sim/fr30/div1.cgs: New testcase.
* sim/fr30/div2.cgs: New testcase.
* sim/fr30/div3.cgs: New testcase.
* sim/fr30/div4s.cgs: New testcase.
* sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
Tue Dec 8 13:16:53 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/testutils.inc (set_s_user): Correct Mask.
(set_s_system): Correct Mask.
* sim/fr30/ld.cgs (ld): Move previously failing test back
into place.
* sim/fr30/ldm0.cgs: New testcase.
* sim/fr30/ldm1.cgs: New testcase.
* sim/fr30/stm0.cgs: New testcase.
* sim/fr30/stm1.cgs: New testcase.
Thu Dec 3 14:20:03 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/ld.cgs: Implement more loads.
* sim/fr30/call.cgs: New testcase.
* sim/fr30/testutils.inc (testr_h_dr): New macro.
(set_s_user,set_s_system): New macros.
* sim/fr30: New Directory.
Wed Nov 18 10:50:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
* common/bits-gen.c (main): Add BYTE_ORDER so that it matches
recent sim/common/sim-basics.h changes.
* common/Makefile.in: Update.
Fri Oct 30 00:37:31 1998 Felix Lee <flee@cygnus.com>
* lib/sim-defs.exp (sim_run): download target program to remote
host, if necessary. for unix-driven win32 testing.
Tue Sep 15 14:56:22 1998 Doug Evans <devans@canuck.cygnus.com>
* sim/m32r/testutils.inc (test_h_gr): Use mvaddr_h_gr.
* sim/m32r/rte.cgs: Test bbpc,bbpsw.
* sim/m32r/trap.cgs: Test bbpc,bbpsw.
Fri Jul 31 17:49:13 1998 Felix Lee <flee@cygnus.com>
* lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of
writeonly.
Fri Jul 24 09:40:34 1998 Doug Evans <devans@canuck.cygnus.com>
* Makefile.in (clean,mostlyclean): Change leading spaces to a tab.
Wed Jul 1 15:57:54 1998 Doug Evans <devans@seba.cygnus.com>
* sim/m32r/hw-trap.ms: New testcase.
Tue Jun 16 15:44:01 1998 Jillian Ye <jillian@cygnus.com>
* lib/sim-defs.exp: Print out timeout setting info when "-v" is used.
Thu Jun 11 15:24:53 1998 Doug Evans <devans@canuck.cygnus.com>
* lib/sim-defs.exp (sim_run): Argument env_vals renamed to options,
which is now a list of options controlling the behaviour of sim_run.
Wed Jun 10 10:53:20 1998 Doug Evans <devans@seba.cygnus.com>
* sim/m32r/addx.cgs: Add another test.
* sim/m32r/jmp.cgs: Add another test.
Mon Jun 8 16:08:27 1998 Doug Evans <devans@canuck.cygnus.com>
* sim/m32r/trap.cgs: Test trap 2.
Mon Jun 1 18:54:22 1998 Frank Ch. Eigler <fche@cygnus.com>
* lib/sim-defs.exp (sim_run): Add possible environment variable
list to simulator run.
Thu May 28 14:59:46 1998 Jillian Ye <jillian@cygnus.com>
* Makefile.in: Take RUNTEST out of FLAG_TO_PASS
so that make check can be invoked recursively.
Thu May 14 11:48:35 1998 Doug Evans <devans@canuck.cygnus.com>
* config/default.exp (CC,SIM): Delete.
* lib/sim-defs.exp (sim_run): Fix handling of output redirection.
New arg prog_opts. All callers updated.
Fri May 8 18:10:28 1998 Jillian Ye <jillian@cygnus.com>
* Makefile.in: Made "check" the target of two
dependencies (test1, test2) so that test2 get a chance to
run even when test1 failed if "make -k check" is used.
Fri May 8 14:41:28 1998 Doug Evans <devans@canuck.cygnus.com>
* lib/sim-defs.exp (sim_version): Simplify.
(sim_run): Implement.
(run_sim_test): Use sim_run.
(sim_compile): New proc.
Mon May 4 17:59:11 1998 Frank Ch. Eigler <fche@cygnus.com>
* config/default.exp: Added C compiler settings.
Wed Apr 22 12:26:28 1998 Doug Evans <devans@canuck.cygnus.com>
* Makefile.in (TARGET_FLAGS_TO_PASS): Delete LIBS, LDFLAGS.
Tue Apr 21 10:49:03 1998 Doug Evans <devans@canuck.cygnus.com>
* lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails,
try all machs.
* sim/m32r/addx.cgs: Test (-1)+(-1)+1.
Fri Apr 17 16:00:52 1998 Doug Evans <devans@canuck.cygnus.com>
* sim/m32r/mv[ft]achi.cgs: Fix expected result
(sign extension of top 8 bits).
Wed Feb 25 11:01:17 1998 Doug Evans <devans@canuck.cygnus.com>
* Makefile.in (RUNTEST): Fix path to runtest.
Fri Feb 20 11:00:02 1998 Nick Clifton <nickc@cygnus.com>
* sim/m32r/unlock.cgs: Fixed test.
* sim/m32r/mvfc.cgs: Fixed test.
* sim/m32r/remu.cgs: Fixed test.
* sim/m32r/bnc24.cgs: Test long BNC instruction.
* sim/m32r/bnc8.cgs: Test short BNC instruction.
* sim/m32r/ld-plus.cgs: Test LD instruction.
* sim/m32r/macwhi.cgs: Test MACWHI instruction.
* sim/m32r/macwlo.cgs: Test MACWLO instruction.
* sim/m32r/mulwhi.cgs: Test MULWHI instruction.
* sim/m32r/mulwlo.cgs: Test MULWLO instruction.
* sim/m32r/mvfachi.cgs: Test MVFACHI instruction.
* sim/m32r/mvfaclo.cgs: Test MVFACLO instruction.
* sim/m32r/mvtaclo.cgs: Test MVTACLO instruction.
* sim/m32r/addv.cgs: Test ADDV instruction.
* sim/m32r/addv3.cgs: Test ADDV3 instruction.
* sim/m32r/addx.cgs: Test ADDX instruction.
* sim/m32r/lock.cgs: Test LOCK instruction.
* sim/m32r/neg.cgs: Test NEG instruction.
* sim/m32r/not.cgs: Test NOT instruction.
* sim/m32r/unlock.cgs: Test UNLOCK instruction.
Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
* sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
address into a general register.
* sim/m32r/or3.cgs: Test OR3 instruction.
* sim/m32r/rach.cgs: Test RACH instruction.
* sim/m32r/rem.cgs: Test REM instruction.
* sim/m32r/sub.cgs: Test SUB instruction.
* sim/m32r/mv.cgs: Test MV instruction.
* sim/m32r/mul.cgs: Test MUL instruction.
* sim/m32r/bl24.cgs: Test long BL instruction.
* sim/m32r/bl8.cgs: Test short BL instruction.
* sim/m32r/blez.cgs: Test BLEZ instruction.
* sim/m32r/bltz.cgs: Test BLTZ instruction.
* sim/m32r/bne.cgs: Test BNE instruction.
* sim/m32r/bnez.cgs: Test BNEZ instruction.
* sim/m32r/bra24.cgs: Test long BRA instruction.
* sim/m32r/bra8.cgs: Test short BRA instruction.
* sim/m32r/jl.cgs: Test JL instruction.
* sim/m32r/or.cgs: Test OR instruction.
* sim/m32r/jmp.cgs: Test JMP instruction.
* sim/m32r/and.cgs: Test AND instruction.
* sim/m32r/and3.cgs: Test AND3 instruction.
* sim/m32r/beq.cgs: Test BEQ instruction.
* sim/m32r/beqz.cgs: Test BEQZ instruction.
* sim/m32r/bgez.cgs: Test BGEZ instruction.
* sim/m32r/bgtz.cgs: Test BGTZ instruction.
* sim/m32r/cmp.cgs: Test CMP instruction.
* sim/m32r/cmpi.cgs: Test CMPI instruction.
* sim/m32r/cmpu.cgs: Test CMPU instruction.
* sim/m32r/cmpui.cgs: Test CMPUI instruction.
* sim/m32r/div.cgs: Test DIV instruction.
* sim/m32r/divu.cgs: Test DIVU instruction.
* sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
* sim/m32r/sll.cgs: Test SLL instruction.
* sim/m32r/sll3.cgs: Test SLL3 instruction.
* sim/m32r/slli.cgs: Test SLLI instruction.
* sim/m32r/sra.cgs: Test SRA instruction.
* sim/m32r/sra3.cgs: Test SRA3 instruction.
* sim/m32r/srai.cgs: Test SRAI instruction.
* sim/m32r/srl.cgs: Test SRL instruction.
* sim/m32r/srl3.cgs: Test SRL3 instruction.
* sim/m32r/srli.cgs: Test SRLI instruction.
* sim/m32r/xor3.cgs: Test XOR3 instruction.
* sim/m32r/xor.cgs: Test XOR instruction.
Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
* config/default.exp: New file.
* lib/sim-defs.exp: New file.
* sim/m32r/*: m32r dejagnu simulator testsuite.
* Makefile.in (build_alias): Define.
(arch): Define.
(RUNTEST_FOR_TARGET): Delete.
(RUNTEST): Fix.
(check): Depend on site.exp. Run dejagnu.
(site.exp): New target.
* configure.in (arch): Define from target_cpu.
* configure: Regenerate.
Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
* common/bits-gen.c (gen_bit): Pass in the full name of the macro.
(gen_mask): Ditto.
* common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
(calc): Add support for 8 bit version of macros.
(main): Add tests for 8 bit versions of macros.
(check_sext): Check SEXT of zero clears bits.
* common/bits-gen.c (main): Generate tests for 8 bit versions of
macros.
Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
* common/Make-common.in: New file, provide generic rules for
running checks.
Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure.in (configdirs): Test for the target directory instead
of matching on a target.
|
