1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
|
/* This file is part of the program psim.
Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CPU_C_
#define _CPU_C_
#ifndef STATIC_INLINE_CPU
#define STATIC_INLINE_CPU STATIC_INLINE
#endif
#include <setjmp.h>
#include "cpu.h"
#include "idecode.h"
struct _cpu {
/* the registers */
registers regs;
/* current instruction address */
unsigned_word program_counter;
/* the memory maps */
core *physical; /* all of memory */
vm *virtual;
vm_instruction_map *instruction_map; /* instructions */
vm_data_map *data_map; /* data */
/* current state of interrupt inputs */
int external_exception_pending;
/* the system this processor is contained within */
psim *system;
event_queue *events;
int cpu_nr;
/* if required, a cache to store decoded instructions */
#if WITH_IDECODE_CACHE
idecode_cache icache[IDECODE_CACHE_SIZE];
#endif
/* address reservation: keep the physical address and the contents
of memory at that address */
memory_reservation reservation;
/* offset from event time to this cpu's idea of the local time */
signed64 time_base_local_time;
signed64 decrementer_local_time;
event_entry_tag decrementer_event;
/* Counts of number of instructions executed. */
long number_of_insns;
};
INLINE_CPU cpu *
cpu_create(psim *system,
core *memory,
event_queue *events,
int cpu_nr)
{
cpu *processor = ZALLOC(cpu);
/* create the virtual memory map from the core */
processor->physical = memory;
processor->virtual = vm_create(memory);
processor->instruction_map = vm_create_instruction_map(processor->virtual);
processor->data_map = vm_create_data_map(processor->virtual);
/* link back to core system */
processor->system = system;
processor->events = events;
processor->cpu_nr = cpu_nr;
return processor;
}
/* find ones way home */
INLINE_CPU psim *
cpu_system(cpu *processor)
{
return processor->system;
}
INLINE_CPU int
cpu_nr(cpu *processor)
{
return processor->cpu_nr;
}
INLINE_CPU event_queue *
cpu_event_queue(cpu *processor)
{
return processor->events;
}
/* The processors local concept of time */
INLINE_CPU signed64
cpu_get_time_base(cpu *processor)
{
return (event_queue_time(processor->events)
+ processor->time_base_local_time);
}
INLINE_CPU void
cpu_set_time_base(cpu *processor,
signed64 time_base)
{
processor->time_base_local_time = (event_queue_time(processor->events)
- time_base);
}
INLINE_CPU signed32
cpu_get_decrementer(cpu *processor)
{
return (processor->decrementer_local_time
- event_queue_time(processor->events));
}
STATIC_INLINE_CPU void
cpu_decrement_event(event_queue *queue,
void *data)
{
cpu *processor = (cpu*)data;
if (!decrementer_interrupt(processor)) {
processor->decrementer_event = event_queue_schedule(processor->events,
1, /* NOW! */
cpu_decrement_event,
processor);
}
}
INLINE_CPU void
cpu_set_decrementer(cpu *processor,
signed32 decrementer)
{
signed64 old_decrementer = (processor->decrementer_local_time
- event_queue_time(processor->events));
event_queue_deschedule(processor->events, processor->decrementer_event);
processor->decrementer_local_time = (event_queue_time(processor->events)
+ decrementer);
if (decrementer < 0 && old_decrementer >= 0)
/* dec interrupt occures if the sign of the decrement reg is
changed by the load operation */
processor->decrementer_event = event_queue_schedule(processor->events,
1, /* NOW! */
cpu_decrement_event,
processor);
else if (decrementer >= 0)
processor->decrementer_event = event_queue_schedule(processor->events,
decrementer,
cpu_decrement_event,
processor);
}
/* program counter manipulation */
INLINE_CPU void
cpu_set_program_counter(cpu *processor,
unsigned_word new_program_counter)
{
processor->program_counter = new_program_counter;
}
INLINE_CPU unsigned_word
cpu_get_program_counter(cpu *processor)
{
return processor->program_counter;
}
INLINE_CPU void
cpu_restart(cpu *processor,
unsigned_word nia)
{
processor->program_counter = nia;
psim_restart(processor->system, processor->cpu_nr);
}
INLINE_CPU void
cpu_halt(cpu *processor,
unsigned_word cia,
stop_reason reason,
int signal)
{
processor->program_counter = cia;
psim_halt(processor->system, processor->cpu_nr, cia, reason, signal);
}
#if WITH_IDECODE_CACHE
/* allow access to the cpu's instruction cache */
INLINE_CPU idecode_cache *
cpu_icache(cpu *processor)
{
return processor->icache;
}
#endif
/* address map revelation */
INLINE_CPU vm_instruction_map *
cpu_instruction_map(cpu *processor)
{
return processor->instruction_map;
}
INLINE_CPU vm_data_map *
cpu_data_map(cpu *processor)
{
return processor->data_map;
}
INLINE_CPU core *
cpu_core(cpu *processor)
{
return processor->physical;
}
/* reservation access */
INLINE_CPU memory_reservation *
cpu_reservation(cpu *processor)
{
return &processor->reservation;
}
/* register access */
INLINE_CPU registers *
cpu_registers(cpu *processor)
{
return &processor->regs;
}
INLINE_CPU void
cpu_synchronize_context(cpu *processor)
{
#if WITH_IDECODE_CACHE
/* kill off the contents of the cache */
int i;
for (i = 0; i < IDECODE_CACHE_SIZE; i++)
processor->icache[i].address = MASK(0,63);
#endif
vm_synchronize_context(processor->virtual,
processor->regs.spr,
processor->regs.sr,
processor->regs.msr);
}
/* # of instructions counter access */
INLINE_CPU void
cpu_increment_number_of_insns(cpu *processor)
{
processor->number_of_insns++;
}
INLINE_CPU long
cpu_get_number_of_insns(cpu *processor)
{
return processor->number_of_insns;
}
INLINE_CPU void
cpu_print_info(cpu *processor, int verbose)
{
printf_filtered("CPU #%d executed %ld instructions.\n",
processor->cpu_nr+1,
processor->number_of_insns);
}
#endif /* _CPU_C_ */
|