path: root/sim/mips/ChangeLog

2002-06-07  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c: Clean up formatting of a few comments.
	(value_fpr): Reformat switch statement.

2002-06-06  Chris Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* cp1.h: New file.
	* sim-main.h: Include cp1.h.
	(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
	(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
	(FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
	(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
	(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
	(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
	* cp1.c: Don't include sim-fpu.h; already included by
	sim-main.h.  Clean up formatting of some comments.
	(NaN, Equal, Less): Remove.
	(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
	(fp_cmp): New functions.
	* mips.igen (do_c_cond_fmt): Remove.
	(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
	Compare.  Add result tracing.
	(CxC1): Remove, replace with...
	(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
	(DMxC1): Remove, replace with...
	(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
	(MxC1): Remove, replace with... 
	(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.  

2002-06-04  Chris Demetriou  <cgd@broadcom.com>

	* sim-main.h (FGRIDX): Remove, replace all uses with...
	(FGR_BASE): New macro.
	(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
	(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
	(NR_FGR, FGR): Likewise.
	* interp.c: Replace all uses of FGRIDX with FGR_BASE.
	* mips.igen: Likewise.

2002-06-04  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c: Add an FSF Copyright notice to this file.

2002-06-04  Chris Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* cp1.c (Infinity): Remove.
	* sim-main.h (Infinity): Likewise.

	* cp1.c (fp_unary, fp_binary): New functions.
	(fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
	(fp_sqrt): New functions, implemented in terms of the above.
	(AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
	(Recip, SquareRoot): Remove (replaced by functions above).
	* sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
	(fp_recip, fp_sqrt): New prototypes.
	(AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
	(Recip, SquareRoot): Replace prototypes with #defines which
	invoke the functions above.
	
2002-06-03  Chris Demetriou  <cgd@broadcom.com>

	* sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
	(Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
	file, remove PARAMS from prototypes.
	(value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
	simulator state arguments.
	(ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
	pass simulator state arguments.
	* cp1.c (SD): Redefine as CPU_STATE(cpu).
	(store_fpr, convert): Remove 'sd' argument.
	(value_fpr): Likewise.  Convert to use 'SD' instead.

2002-06-03  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c (Min, Max): Remove #if 0'd functions.
	* sim-main.h (Min, Max): Remove.

2002-06-03  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c: fix formatting of switch case and default labels.
	* interp.c: Likewise.
	* sim-main.c: Likewise.

2002-06-03  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c: Clean up comments which describe FP formats.
	 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.

2002-06-03  Chris Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* configure.in (mipsisa64sb1*-*-*): New target for supporting
	Broadcom SiByte SB-1 processor configurations.
	* configure: Regenerate.
	* sb1.igen: New file.
	* mips.igen: Include sb1.igen.
	(sb1): New model.
	* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
	* mdmx.igen: Add "sb1" model to all appropriate functions and
	instructions.
	* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
	(ob_func, ob_acc): Reference the above.
	(qh_acc): Adjust to keep the same size as ob_acc.
	* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
	(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.

2002-06-03  Chris Demetriou  <cgd@broadcom.com>

	* Makefile.in (IGEN_INCLUDE): Add mdmx.igen.

2002-06-02  Chris Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* mips.igen (mdmx): New (pseudo-)model.
	* mdmx.c, mdmx.igen: New files.
	* Makefile.in (SIM_OBJS): Add mdmx.o.
	* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
	New typedefs.
	(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
	(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
	(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
	(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
	(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
	(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
	(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
	(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
	(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
	(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
	(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
	(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
	(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
	(qh_fmtsel): New macros.
	(_sim_cpu): New member "acc".
	(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
	(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.

2002-05-01  Chris Demetriou  <cgd@broadcom.com>

	* interp.c: Use 'deprecated' rather than 'depreciated.'
	* sim-main.h: Likewise.

2002-05-01  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
	which wouldn't compile anyway.
	* sim-main.h (unpredictable_action): New function prototype.
	(Unpredictable): Define to call igen function unpredictable().
	(NotWordValue): New macro to call igen function not_word_value().
	(UndefinedResult): Remove.
	* interp.c (undefined_result): Remove.
	(unpredictable_action): New function.
	* mips.igen (not_word_value, unpredictable): New functions.
	(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
	(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
	(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
	NotWordValue() to check for unpredictable inputs, then
	Unpredictable() to handle them.

2002-02-24  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen: Fix formatting of calls to Unpredictable().

2002-04-20  Andrew Cagney  <ac131313@redhat.com>

	* interp.c (sim_open): Revert previous change.

2002-04-18  Alexandre Oliva  <aoliva@redhat.com>

	* interp.c (sim_open): Disable chunk of code that wrote code in
	vector table entries.

2002-03-19  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
	(FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
	unused definitions.

2002-03-19  Chris Demetriou  <cgd@broadcom.com>

	* cp1.c: Fix many formatting issues.

2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>

	* cp1.c (fpu_format_name): New function to replace...
	(DOFMT): This.  Delete, and update all callers.
	(fpu_rounding_mode_name): New function to replace...
	(RMMODE): This.  Delete, and update all callers.

2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>

	* interp.c: Move FPU support routines from here to...
	* cp1.c: Here.  New file.
	* Makefile.in (SIM_OBJS): Add cp1.o to object list.
	(cp1.o): New target.

2002-03-12  Chris Demetriou  <cgd@broadcom.com>

	* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
	* mips.igen (mips32, mips64): New models, add to all instructions
	and functions as appropriate.
	(loadstore_ea, check_u64): New variant for model mips64.
	(check_fmt_p): New variant for models mipsV and mips64, remove
	mipsV model marking fro other variant.
	(SLL) Rename to...
	(SLLa) this.
	(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
	for mips32 and mips64.
	(DCLO, DCLZ): New instructions for mips64.

2002-03-07  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
	immediate or code as a hex value with the "%#lx" format.
	(ANDI): Likewise, and fix printed instruction name.

2002-03-05  Chris Demetriou  <cgd@broadcom.com>

	* sim-main.h (UndefinedResult, Unpredictable): New macros
	which currently do nothing.

2002-03-05  Chris Demetriou  <cgd@broadcom.com>

	* sim-main.h (status_UX, status_SX, status_KX, status_TS)
	(status_PX, status_MX, status_CU0, status_CU1, status_CU2)
	(status_CU3): New definitions.

	* sim-main.h (ExceptionCause): Add new values for MIPS32
	and MIPS64: MDMX, MCheck, CacheErr.  Update comments
	for DebugBreakPoint and NMIReset to note their status in
	MIPS32 and MIPS64.
	(SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
	(SignalExceptionCacheErr): New exception macros.

2002-03-05  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
	* sim-main.h (COP_Usable): Define, but for now coprocessor 1
	is always enabled.
	(SignalExceptionCoProcessorUnusable): Take as argument the
	unusable coprocessor number.

2002-03-05  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen: Fix formatting of all SignalException calls.

2002-03-05  Chris Demetriou  <cgd@broadcom.com>

	* sim-main.h (SIGNEXTEND): Remove.

2002-03-04  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen: Remove gencode comment from top of file, fix
	spelling in another comment.

2002-03-04  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (check_fmt, check_fmt_p): New functions to check
	whether specific floating point formats are usable.
	(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
	(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
	(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
	Use the new functions.
	(do_c_cond_fmt): Remove format checks...
	(C.cond.fmta, C.cond.fmtb): And move them into all callers.

2002-03-03  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen: Fix formatting of check_fpu calls.

2002-03-03  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (FLOOR.L.fmt): Store correct destination register.

2002-03-03  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen: Remove whitespace at end of lines.

2002-03-02  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (loadstore_ea): New function to do effective
	address calculations.
	(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
	do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
	CACHE): Use loadstore_ea to do effective address computations.

2002-03-02  Chris Demetriou  <cgd@broadcom.com>

	* interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
	* mips.igen (LL, CxC1, MxC1): Likewise.

2002-03-02  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
	CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
	FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
	MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
	NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
	SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
	Don't split opcode fields by hand, use the opcode field values
	provided by igen.

2002-03-01  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (do_divu): Fix spacing.

	* mips.igen (do_dsllv): Move to be right before DSLLV,
	to match the rest of the do_<shift> functions.

2002-03-01  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
	DSRL32, do_dsrlv): Trace inputs and results.

2002-03-01  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (CACHE): Provide instruction-printing string.

	* interp.c (signal_exception): Comment tokens after #endif.

2002-02-28  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
	(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt, 
	NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt, 
	ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt, 
	CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta, 
	C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1, 
	SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D, 
	LWC1, SWC1): Add "f" to filter, since these are FP instructions.

2002-02-28  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (DSRA32, DSRAV): Fix order of arguments in
	instruction-printing string.
	(LWU): Use '64' as the filter flag.

2002-02-28  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (SDXC1): Fix instruction-printing string.

2002-02-28  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
	filter flags "32,f".

2002-02-27  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (PREFX): This is a 64-bit instruction, use '64'
	as the filter flag.

2002-02-27  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
	add a comma) so that it more closely match the MIPS ISA
	documentation opcode partitioning.
	(PREF): Put useful names on opcode fields, and include
	instruction-printing string.

2002-02-27  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (check_u64): New function which in the future will
	check whether 64-bit instructions are usable and signal an
	exception if not.  Currently a no-op.
	(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
	DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
	DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
	LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.

	* mips.igen (check_fpu): New function which in the future will
	check whether FPU instructions are usable and signal an exception
	if not.  Currently a no-op.
	(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
	CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
	CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
	LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
	MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
	NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
	ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
	SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.

2002-02-27  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (do_load_left, do_load_right): Move to be immediately
	following do_load.
	(do_store_left, do_store_right): Move to be immediately following
	do_store.

2002-02-27  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (mipsV): New model name.  Also, add it to
	all instructions and functions where it is appropriate.

2002-02-18  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen: For all functions and instructions, list model
	names that support that instruction one per line.

2002-02-11  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen: Add some additional comments about supported
	models, and about which instructions go where.
	(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
	order as is used in the rest of the file.

2002-02-11  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
	indicating that ALU32_END or ALU64_END are there to check
	for overflow.
	(DADD): Likewise, but also remove previous comment about
	overflow checking.

2002-02-10  Chris Demetriou  <cgd@broadcom.com>

	* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
	DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
	JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
	SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
	ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
	fields (i.e., add and move commas) so that they more closely
	match the MIPS ISA documentation opcode partitioning.

2002-02-10  Chris Demetriou  <cgd@broadcom.com>

        * mips.igen (ADDI): Print immediate value.
        (BREAK): Print code.
        (DADDIU, DSRAV, DSRLV): Print correct instruction name.
        (SLL): Print "nop" specially, and don't run the code
        that does the shift for the "nop" case.

2001-11-17  Fred Fish  <fnf@redhat.com>

	* sim-main.h (float_operation): Move enum declaration outside
	of _sim_cpu struct declaration.

2001-04-12  Jim Blandy  <jimb@redhat.com>

	* mips.igen (CFC1, CTC1): Pass the correct register numbers to
	PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
	set of the FCSR.
	* sim-main.h (COCIDX): Remove definition; this isn't supported by
	PENDING_FILL, and you can get the intended effect gracefully by
	calling PENDING_SCHED directly.

2001-02-23  Ben Elliston  <bje@redhat.com>

	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
	already defined elsewhere.

2001-02-19  Ben Elliston  <bje@redhat.com>

	* sim-main.h (sim_monitor): Return an int.
	* interp.c (sim_monitor): Add return values.
	(signal_exception): Handle error conditions from sim_monitor.

2001-02-08  Ben Elliston  <bje@redhat.com>

	* sim-main.c (load_memory): Pass cia to sim_core_read* functions.
	(store_memory): Likewise, pass cia to sim_core_write*.

2000-10-19  Frank Ch. Eigler  <fche@redhat.com>

	On advice from Chris G. Demetriou <cgd@sibyte.com>:
	* sim-main.h (GPR_CLEAR): Remove unused alternative macro.

Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
	* Makefile.in: Don't delete *.igen when cleaning directory.

Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	* m16.igen (break): Call SignalException not sim_engine_halt.

Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	From Jason Eckhardt:
	* mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].

Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (MxC1, DMxC1): Fix printf formatting.

2000-05-24  Michael Hayes  <mhayes@cygnus.com>

	* mips.igen (do_dmultx): Fix typo.

Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.

2000-04-12  Frank Ch. Eigler  <fche@redhat.com>

	* sim-main.h (GPR_CLEAR): Define macro.

Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (decode_coproc): Output long using %lx and not %s.

2000-03-21  Frank Ch. Eigler  <fche@redhat.com>

	* interp.c (sim_open): Sort & extend dummy memory regions for
	--board=jmr3904 for eCos.

2000-03-02  Frank Ch. Eigler  <fche@redhat.com>

	* configure: Regenerated.

Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>

	* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
	calls, conditional on the simulator being in verbose mode.

Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>

	* sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
	cache don't get ReservedInstruction traps.

1999-11-29  Mark Salter  <msalter@cygnus.com>

	* dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
	to clear status bits in sdisr register. This is how the hardware works.

	* interp.c (sim_open): Added more memory aliases for jmr3904 hardware
	being used by cygmon.

1999-11-11  Andrew Haley  <aph@cygnus.com>

	* interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
	instructions.

Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>

	* mips.igen (MULT): Correct previous mis-applied patch.

Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>

	* mips.igen (delayslot32): Handle sequence like
	mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
	correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
	(MULT): Actually pass the third register...

1999-09-03  Mark Salter  <msalter@cygnus.com>

	* interp.c (sim_open): Added more memory aliases for additional
	hardware being touched by cygmon on jmr3904 board.

Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>

	* interp.c (sim_store_register): Handle case where client - GDB -
 	specifies that a 4 byte register is 8 bytes in size.
	(sim_fetch_register): Ditto.
	
1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>

	Implement "sim firmware" option, inspired by jimb's version of 1998-01.
	* interp.c (firmware_option_p): New global flag: "sim firmware" given.
	(idt_monitor_base): Base address for IDT monitor traps.
	(pmon_monitor_base): Ditto for PMON.
	(lsipmon_monitor_base): Ditto for LSI PMON.
	(MONITOR_BASE, MONITOR_SIZE): Removed macros.
	(mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
	(sim_firmware_command): New function.
	(mips_option_handler): Call it for OPTION_FIRMWARE.
	(sim_open): Allocate memory for idt_monitor region.  If "--board"
	option was given, add no monitor by default.  Add BREAK hooks only if
	monitors are also there.
	
Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>

	* interp.c (sim_monitor): Flush output before reading input.

Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>

	* tconfig.in (SIM_HANDLES_LMA): Always define.

Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>

	From Mark Salter <msalter@cygnus.com>:
	* interp.c (BOARD_BSP): Define.  Add to list of possible boards.
	(sim_open): Add setup for BSP board.

Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (MULT, MULTU): Add syntax for two operand version.
	(DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 	them as unimplemented.

1999-05-08  Felix Lee  <flee@cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	
1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>

	* mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.

Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>

	* configure.in: Any mips64vr5*-*-* target should have
 	-DTARGET_ENABLE_FR=1.
	(default_endian): Any mips64vr*el-*-* target should default to
	LITTLE_ENDIAN.
	* configure: Re-generate.

1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>

	* mips.igen (ldl): Extend from _16_, not 32.

Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>

	* interp.c (sim_store_register): Force registers written to by GDB
 	into an un-interpreted state.

1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 	CPU, start periodic background I/O polls.
	(tx3904sio_poll): New function: periodic I/O poller. 

1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>

	* mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
	
Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>

	* configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 	case statement.

1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
	
	* interp.c (sim_open): Allocate jm3904 memory in smaller chunks. 
	(load_word): Call SIM_CORE_SIGNAL hook on error.
	(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
	starting.  For exception dispatching, pass PC instead of NULL_CIA.
	(decode_coproc): Use COP0_BADVADDR to store faulting address.
	* sim-main.h (COP0_BADVADDR): Define. 
	(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
	(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
	(_sim_cpu): Add exc_* fields to store register value snapshots.	
	* mips.igen (*): Replace memory-related SignalException* calls
	with references to SIM_CORE_SIGNAL hook.
	
	* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
	fix.
	* sim-main.c (*): Minor warning cleanups.
	
1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>

	* m16.igen (DADDIU5): Correct type-o.

Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>

	* mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 	variables.

Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>

	* Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 	to include path.
	(interp.o): Add dependency on itable.h
	(oengine.c, gencode): Delete remaining references.
	(BUILT_SRC_FROM_GEN): Clean up.
	
1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
	
	* vr4run.c: New.
	* Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
	tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
	tmp-run-hack) : New.
	* m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
	DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): 
	Drop the "64" qualifier to get the HACK generator working.
	Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
	* mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
	qualifier to get the hack generator working.
	(do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
	(DSLL): Use do_dsll.
	(DSLLV): Use do_dsllv.
	(DSRA): Use do_dsra.
	(DSRL): Use do_dsrl.
	(DSRLV): Use do_dsrlv.
	(BC1): Move *vr4100 to get the HACK generator working.
	(CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to 
	get the HACK generator working.
	(MACC) Rename to get the HACK generator working.
	(DMACC,MACCS,DMACCS): Add the 64.
	
1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>

	* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
	* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
	
1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>

    * mips/interp.c (DEBUG): Cleanups.

1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
	(tx3904sio_tickle): fflush after a stdout character output.
	
1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (sim_close): Uninstall modules.

Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h, interp.c (sim_monitor): Change to global
 	function.

Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in (vr4100): Only include vr4100 instructions in
 	simulator.
	* configure: Re-generate.
	* m16.igen (*): Tag all mips16 instructions as also being vr4100.

Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
	* sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 	true alternative.

	* configure.in (sim_default_gen, sim_use_gen): Replace with
 	sim_gen.
	(--enable-sim-igen): Delete config option. Always using IGEN.
	* configure: Re-generate.
	
	* Makefile.in (gencode): Kill, kill, kill.
	* gencode.c: Ditto.
	
Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 	bit mips16 igen simulator.
	* configure: Re-generate.

	* mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 	as part of vr4100 ISA.
	* vr.igen: Mark all instructions as 64 bit only.

Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 	Pacify GCC.

Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 	mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
	* configure: Re-generate.

	* m16.igen (BREAK): Define breakpoint instruction.
	(JALX32): Mark instruction as mips16 and not r3900.
	* mips.igen (C.cond.fmt): Fix typo in instruction format.

	* sim-main.h (PENDING_FILL): Wrap C statements in do/while.

Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 	insn as a debug breakpoint.

	* sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 	pending.slot_size.
	(PENDING_SCHED): Clean up trace statement.
	(PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
	(PENDING_FILL): Delay write by only one cycle.
	(PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.

	* sim-main.c (pending_tick): Clean up trace statements. Add trace
 	of pending writes.
	(pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 	32 & 64.
	(pending_tick): Move incrementing of index to FOR statement.
	(pending_tick): Only update PENDING_OUT after a write has occured.
	
	* configure.in: Add explicit mips-lsi-* target.  Use gencode to
 	build simulator.
	* configure: Re-generate.
	
	* interp.c (sim_engine_run OLD): Delete explicit call to
 	PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
	
Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
	interrupt level number to match changed SignalExceptionInterrupt
	macro.

Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>

	* interp.c: #include "itable.h" if WITH_IGEN.
	(get_insn_name): New function.
	(sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
	* sim-main.h (MAX_INSNS,INSN_NAME): Delete.

Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* configure: Rebuilt to inhale new common/aclocal.m4.

Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904sio.c: Include sim-assert.h.

Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904sio.c: New file: tx3904 serial I/O module.
	* configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
	Reorganize target-specific sim-hardware checks.
	* configure: rebuilt.
	* interp.c (sim_open): For tx39 target boards, set
	OPERATING_ENVIRONMENT, add tx3904sio devices.
	* tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
	ROM executables.  Install dv-sockser into sim-modules list.
	
	* dv-tx3904irc.c: Compiler warning clean-up.
	* dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
	frequent hw-trace messages.

Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* vr.igen (MulAcc): Identify as a vr4100 specific function.

Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (IGEN_INCLUDE): Add vr.igen.

	* vr.igen: New file.
	(MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
	* mips.igen: Define vr4100 model. Include vr.igen.
Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>

	* mips.igen (check_mf_hilo): Correct check.

Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (interrupt_event): Add prototype.

	* dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 	register_ptr, register_value.
	(deliver_tx3904tmr_tick): Fix types passed to printf fmt.

	* sim-main.h (tracefh): Make extern.

Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904tmr.c: Deschedule timer event after dispatching.
	Reduce unnecessarily high timer event frequency.  
	* dv-tx3904cpu.c: Ditto for interrupt event.
	
Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 	to allay warnings.
	(interrupt_event): Made non-static.
	
	* dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 	interchange of configuration values for external vs. internal
 	clock dividers.
	
Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>

	* mips.igen (BREAK): Moved code to here for 
	simulator-reserved break instructions.
	* gencode.c (build_instruction): Ditto.
	* interp.c (signal_exception): Code moved from here.  Non-
	reserved instructions now use exception vector, rather 
	than halting sim.
	* sim-main.h: Moved magic constants to here.

Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 	register upon non-zero interrupt event level, clear upon zero
 	event value.
	* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
	by passing zero event value.
	(*_io_{read,write}_buffer): Endianness fixes.
	* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
	(deliver_*_tick): Reduce sim event interval to 75% of count interval.

	* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
	serial I/O and timer module at base address 0xFFFF0000.
	
Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>

	* mips.igen (SWC1) : Correct the handling of ReverseEndian 
	and BigEndianCPU.

Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>

	* configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
	parts.
	* configure: Update.

Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* dv-tx3904tmr.c: New file - implements tx3904 timer.
	* dv-tx3904{irc,cpu}.c: Mild reformatting.
	* configure.in: Include tx3904tmr in hw_device list.
	* configure: Rebuilt.
	* interp.c (sim_open): Instantiate three timer instances.
	Fix address typo of tx3904irc instance.

Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>

	* interp.c (signal_exception): SystemCall exception now uses
	the exception vector.

Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (decode_coproc): For TX39, add stub COP0 register #3,
	to allay warnings.

Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.

Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.

	* dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 	sim-main.h. Declare a struct hw_descriptor instead of struct
 	hw_device_descriptor.

Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (do_store_left, do_load_left): Compute nr of left and
 	right bits and then re-align left hand bytes to correct byte
 	lanes.  Fix incorrect computation in do_store_left when loading
 	bytes from second word.

Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
	* interp.c (sim_open): Only create a device tree when HW is
 	enabled.

	* dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
	* interp.c (signal_exception): Ditto.

Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>

	* gencode.c: Mark BEGEZALL as LIKELY.

Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (ALU32_END): Sign extend 32 bit results.
	* mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
	
Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 	modules.  Recognize TX39 target with "mips*tx39" pattern.
	* configure: Rebuilt.
	* sim-main.h (*): Added many macros defining bits in
 	TX39 control registers.
	(SignalInterrupt): Send actual PC instead of NULL.
	(SignalNMIReset): New exception type.
	* interp.c (board): New variable for future use to identify
	a particular board being simulated.
	(mips_option_handler,mips_options): Added "--board" option.
	(interrupt_event): Send actual PC.
	(sim_open): Make memory layout conditional on board setting.
	(signal_exception): Initial implementation of hardware interrupt
 	handling.  Accept another break instruction variant for simulator
 	exit.
	(decode_coproc): Implement RFE instruction for TX39.
	(mips.igen): Decode RFE instruction as such.
	* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
	* interp.c: Define "jmr3904" and "jmr3904debug" board types and
	bbegin to implement memory map.
	* dv-tx3904cpu.c: New file.
	* dv-tx3904irc.c: New file.

Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>

	* mips.igen (check_mt_hilo): Create a separate r3900 version.

Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>

	* tx.igen (madd,maddu):  Replace calls to check_op_hilo
	with calls to check_div_hilo.

Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>

	* mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
	Replace check_op_hilo with check_mult_hilo and check_div_hilo.
	Add special r3900 version of do_mult_hilo.  
	(do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
	with calls to check_mult_hilo.
	(do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
	with calls to check_div_hilo.

Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in (SUBTARGET_R3900): Define for mipstx39 target.
  	Document a replacement.

Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>

	* interp.c (sim_monitor): Make mon_printf work.

Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>

	* sim-main.h (INSN_NAME): New arg `cpu'.

Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>

        * configure: Regenerated to track ../common/aclocal.m4 changes.

Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>

	* acconfig.h: New file.
	* configure.in: Reverted change of Apr 24; use sinclude again.

Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>

	* configure.in: Don't call sinclude.

Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>

	* mips.igen (do_store_left): Pass 0 not NULL to store_memory.

Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (ERET): Implement.

	* interp.c (decode_coproc): Return sign-extended EPC.

	* mips.igen (ANDI, LUI, MFC0): Add tracing code.

	* interp.c (signal_exception): Do not ignore Trap.
	(signal_exception): On TRAP, restart at exception address.
	(HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
	(signal_exception): Update.
	(sim_open): Patch V_COMMON interrupt vector with an abort sequence
 	so that TRAP instructions are caught.

Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (struct hilo_access, struct hilo_history): Define,
 	contains HI/LO access history.
	(struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
	(HIACCESS, LOACCESS): Delete, replace with
	(HIHISTORY, LOHISTORY): New macros.
	(CHECKHILO): Delete all, moved to mips.igen
	
	* gencode.c (build_instruction): Do not generate checks for
 	correct HI/LO register usage.

	* interp.c (old_engine_run): Delete checks for correct HI/LO
 	register usage.

	* mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 	check_mf_cycles): New functions.
	(do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 	do_divu, domultx, do_mult, do_multu): Use.

	* tx.igen ("madd", "maddu"): Use.
	
Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (DSRAV): Use function do_dsrav.
	(SRAV): Use new function do_srav.

	* m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
	(B): Sign extend 11 bit immediate.
	(EXT-B*): Shift 16 bit immediate left by 1.
	(ADDIU*): Don't sign extend immediate value.

Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* m16run.c (sim_engine_run): Restore CIA after handling an event.

	* sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 	functions.

	* mips.igen (delayslot32, nullify_next_insn): New functions.
	(m16.igen): Always include.
	(do_*): Add more tracing.

	* m16.igen (delayslot16): Add NIA argument, could be called by a
 	32 bit MIPS16 instruction.
	
	* interp.c (ifetch16): Move function from here.
	* sim-main.c (ifetch16): To here.
	
	* sim-main.c (ifetch16, ifetch32): Update to match current
 	implementations of LH, LW.
	(signal_exception): Don't print out incorrect hex value of illegal
 	instruction.

Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 	instruction.

	* m16.igen: Implement MIPS16 instructions.
	
	* mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 	do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 	do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 	do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 	do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 	bodies of corresponding code from 32 bit insn to these.  Also used
 	by MIPS16 versions of functions.
	
	* sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
	(IMEM16): Drop NR argument from macro.

Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_OBJS): Add sim-main.o.

	* sim-main.h (address_translation, load_memory, store_memory,
 	cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 	as INLINE_SIM_MAIN.
	(pr_addr, pr_uword64): Declare.
	(sim-main.c): Include when H_REVEALS_MODULE_P.
	
	* interp.c (address_translation, load_memory, store_memory,
 	cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 	from here.
	* sim-main.c: To here. Fix compilation problems.
	
	* configure.in: Enable inlining.
	* configure: Re-config.

Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen: Include tx.igen.
	* Makefile.in (IGEN_INCLUDE): Add tx.igen.
	* tx.igen: New file, contains MADD and MADDU.

	* interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 	the hardwired constant `7'.
	(store_memory): Ditto.
	(LOADDRMASK): Move definition to sim-main.h.

	mips.igen (MTC0): Enable for r3900.
	(ADDU): Add trace.

	mips.igen (do_load_byte): Delete.
	(do_load, do_store, do_load_left, do_load_write, do_store_left,
 	do_store_right): New functions.
	(SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.

	configure.in: Let the tx39 use igen again.
	configure: Update.
	
Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 	not an address sized quantity.  Return zero for cache sizes.

Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (r3900): r3900 does not support 64 bit integer
 	operations.

Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>

	* configure.in (mipstx39*-*-*): Use gencode simulator rather
	than igen one.
	* configure : Rebuild.
	
Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.

Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Regenerated to track ../common/aclocal.m4 changes.

Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (Max, Min): Comment out functions. Not yet used.

Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 	configurable settings for stand-alone simulator.
	
	* configure.in: Added X11 search, just in case.
	
	* configure: Regenerated.

Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_write, sim_read, load_memory, store_memory):
 	Replace sim_core_*_map with read_map, write_map, exec_map resp.

Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (GETFCC): Return an unsigned value.

Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (DIV): Fix check for -1 / MIN_INT.
	(DADD): Result destination is RD not RT.

Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (HIACCESS, LOACCESS): Always define.

	* mdmx.igen (Maxi, Mini): Rename Max, Min.

	* interp.c (sim_info): Delete.

Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>

	* interp.c (DECLARE_OPTION_HANDLER): Use it.
	(mips_option_handler): New argument `cpu'.
	(sim_open): Update call to sim_add_option_table.

Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (CxC1): Add tracing.

Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (Max, Min): Declare.

	* interp.c (Max, Min): New functions.

	* mips.igen (BC1): Add tracing.
	
Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
	
	* interp.c Added memory map for stack in vr4100
	
Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>

	* interp.c (load_memory): Add missing "break"'s.

Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_store_register, sim_fetch_register): Pass in
 	length parameter.  Return -1.

Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>

	* interp.c: Added hardware init hook, fixed warnings.

Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.

Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (ifetch16): New function.

	* sim-main.h (IMEM32): Rename IMEM.
	(IMEM16_IMMED): Define.
	(IMEM16): Define.
	(DELAY_SLOT): Update.
	
	* m16run.c (sim_engine_run): New file.
	
	* m16.igen: All instructions except LB.
	(LB): Call do_load_byte.
	* mips.igen (do_load_byte): New function.
	(LB): Call do_load_byte.

	* mips.igen: Move spec for insn bit size and high bit from here.
	* Makefile.in (tmp-igen, tmp-m16): To here.

	* m16.dc: New file, decode mips16 instructions.

	* Makefile.in (SIM_NO_ALL): Define.
	(tmp-m16): Generate both 16 bit and 32 bit simulator engines.

Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in (mips_fpu_bitsize): For tx39, restrict floating
 	point unit to 32 bit registers.
	* configure: Re-generate.

Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in (sim_use_gen): Make IGEN the default simulator
 	generator for generic 32 and 64 bit mips targets.
	* configure: Re-generate.

Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (SizeFGR): Determine from floating-point and not gpr
 	bitsize.

	* interp.c (sim_fetch_register, sim_store_register): Read/write
 	FGR from correct location.
	(sim_open): Set size of FGR's according to
 	WITH_TARGET_FLOATING_POINT_BITSIZE.
	
	* sim-main.h (FGR): Store floating point registers in a separate
 	array.

Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (ColdReset): Call PENDING_INVALIDATE.

	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.

	* interp.c (pending_tick): New function.  Deliver pending writes.

	* sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
 	PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
 	it can handle mixed sized quantites and single bits.
	
Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (oengine.h): Do not include when building with IGEN.
	(sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
	(sim_info): Ditto for PROCESSOR_64BIT.
	(sim_monitor): Replace ut_reg with unsigned_word.
	(*): Ditto for t_reg.
	(LOADDRMASK): Define.
	(sim_open): Remove defunct check that host FP is IEEE compliant,
 	using software to emulate floating point.
	(value_fpr, ...): Always compile, was conditional on HASFPU.

Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
 	size.

	* interp.c (SD, CPU): Define.
	(mips_option_handler): Set flags in each CPU.
	(interrupt_event): Assume CPU 0 is the one being iterrupted.
	(sim_close): Do not clear STATE, deleted anyway.
	(sim_write, sim_read): Assume CPU zero's vm should be used for
 	data transfers.
	(sim_create_inferior): Set the PC for all processors.
	(sim_monitor, store_word, load_word, mips16_entry): Add cpu
 	argument.
	(mips16_entry): Pass correct nr of args to store_word, load_word.
	(ColdReset): Cold reset all cpu's.
	(signal_exception): Pass cpu to sim_monitor & mips16_entry.
	(sim_monitor, load_memory, store_memory, signal_exception): Use
 	`CPU' instead of STATE_CPU.


	* sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
 	SD or CPU_.
	
	* sim-main.h (signal_exception): Add sim_cpu arg.
	(SignalException*): Pass both SD and CPU to signal_exception.
	* interp.c (signal_exception): Update.
	
	* sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
 	Ditto
	(sync_operation, prefetch, cache_op, store_memory, load_memory,
 	address_translation): Ditto
	(decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
	
Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_engine_run): Add `nr_cpus' argument.

	* mips.igen (model): Map processor names onto BFD name.	

	* sim-main.h (CPU_CIA): Delete.
 	(SET_CIA, GET_CIA): Define

Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (GPR_SET): Define, used by igen when zeroing a
 	regiser.

	* configure.in (default_endian): Configure a big-endian simulator
 	by default.
	* configure: Re-generate.
	
Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>

	* interp.c (sim_monitor): Handle Densan monitor outbyte
	and inbyte functions.

1997-12-29  Felix Lee  <flee@cygnus.com>

	* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).

Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)

	* Makefile.in (tmp-igen): Arrange for $zero to always be
	reset to zero after every instruction.

Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)

	* mips.igen (MSUB): Fix to work like MADD.
	* gencode.c (MSUB): Similarly.

Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen (LWC1): Correct assembler - lwc1 not swc1.

Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (sim-fpu.h): Include.

	* interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
 	Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
 	using host independant sim_fpu module.

Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (signal_exception): Report internal errors with SIGABRT
 	not SIGQUIT.

	* sim-main.h (C0_CONFIG): New register.
	(signal.h): No longer include.

	* interp.c (decode_coproc): Allow access C0_CONFIG to register.

Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>

	* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).

Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen: Tag vr5000 instructions.
	(ANDI): Was missing mipsIV model, fix assembler syntax.
	(do_c_cond_fmt): New function.
	(C.cond.fmt): Handle mips I-III which do not support CC field
 	separatly.
	(bc1): Handle mips IV which do not have a delaed FCC separatly.
	(SDR): Mask paddr when BigEndianMem, not the converse as specified
 	in IV3.2 spec.
	(DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
 	vr5000 which saves LO in a GPR separatly.
	
	* configure.in (enable-sim-igen): For vr5000, select vr5000
 	specific instructions.
	* configure: Re-generate.
	
Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_OBJS): Add sim-fpu module.

	* interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
 	fmt_uninterpreted_64 bit cases to switch.  Convert to
 	fmt_formatted,

	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,

	* mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
 	as specified in IV3.2 spec.
	(MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.

Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen: Delay slot branches add OFFSET to NIA not CIA.
 	(MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
	(MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
 	PENDING_FILL versions of instructions.  Simplify.
	(X): New function.
	(MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
 	instructions.
	(BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
 	a signed value.
	(MTHI, MFHI): Disable code checking HI-LO.
	
	* sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
 	global.
	(NULLIFY_NEXT_INSTRUCTION): Call dotrace.

Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* gencode.c (build_mips16_operands): Replace IPC with cia.

	* interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
 	value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
 	IPC to `cia'.
	(UndefinedResult): Replace function with macro/function
 	combination.
	(sim_engine_run): Don't save PC in IPC.

	* sim-main.h (IPC): Delete.


	* interp.c (signal_exception, store_word, load_word,
 	address_translation, load_memory, store_memory, cache_op,
 	prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
 	cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
 	current instruction address - cia - argument.
	(sim_read, sim_write): Call address_translation directly.
	(sim_engine_run): Rename variable vaddr to cia.
	(signal_exception): Pass cia to sim_monitor
	
	* sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
 	Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
 	COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.

	* sim-main.h (SignalExceptionSimulatorFault): Delete definition.
  	* interp.c (sim_open): Replace SignalExceptionSimulatorFault with
 	SIM_ASSERT.
	
	* interp.c (signal_exception): Pass restart address to
 	sim_engine_restart.

	* Makefile.in (semantics.o, engine.o, support.o, itable.o,
 	idecode.o): Add dependency.

	* sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
 	Delete definitions
	(DELAY_SLOT): Update NIA not PC with branch address.
	(NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.

	* mips.igen: Use CIA not PC in branch calculations.
	(illegal): Call SignalException.
 	(BEQ, ADDIU): Fix assembler.

Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* m16.igen (JALX): Was missing.

	* configure.in (enable-sim-igen): New configuration option.
	* configure: Re-generate.
	
	* sim-main.h (MAX_INSNS, INSN_NAME): Define.

	* interp.c (load_memory, store_memory): Delete parameter RAW.
	(sim_read, sim_write): Use sim_core_{read,write}_buffer directly
 	bypassing {load,store}_memory.

	* sim-main.h (ByteSwapMem): Delete definition.

	* Makefile.in (SIM_OBJS): Add sim-memopt module.

	* interp.c (sim_do_command, sim_commands): Delete mips specific
 	commands.  Handled by module sim-options.
		
	* sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
	(WITH_MODULO_MEMORY): Define.

	* interp.c (sim_info): Delete code printing memory size.

	* interp.c (mips_size): Nee sim_size, delete function.
	(power2): Delete.
	(monitor, monitor_base, monitor_size): Delete global variables.
	(sim_open, sim_close): Delete code creating monitor and other
 	memory regions.  Use sim-memopts module, via sim_do_commandf, to
 	manage memory regions.
	(load_memory, store_memory): Use sim-core for memory model.
	
	* interp.c (address_translation): Delete all memory map code
 	except line forcing 32 bit addresses.

Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (WITH_TRACE): Delete definition.  Enables common
 	trace options.

	* interp.c (logfh, logfile): Delete globals.
	(sim_open, sim_close): Delete code opening & closing log file.
	(mips_option_handler): Delete -l and -n options.
	(OPTION mips_options): Ditto.

	* interp.c (OPTION mips_options): Rename option trace to dinero.
	(mips_option_handler): Update.

Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (fetch_str): New function.
	(sim_monitor): Rewrite using sim_read & sim_write.
	(sim_open): Check magic number.
	(sim_open): Write monitor vectors into memory using sim_write.
	(MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
	(sim_read, sim_write): Simplify - transfer data one byte at a
 	time.
	(load_memory, store_memory): Clarify meaning of parameter RAW.

	* sim-main.h (isHOST): Defete definition.
	(isTARGET): Mark as depreciated.
	(address_translation): Delete parameter HOST.

	* interp.c (address_translation): Delete parameter HOST.

Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen: 

	* Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
	(tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.

Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* mips.igen: Add model filter field to records.

Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
	
	interp.c (sim_engine_run): Do not compile function sim_engine_run
 	when WITH_IGEN == 1.

	* configure.in (sim_igen_flags, sim_m16_flags): Set according to
 	target architecture.

	Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
 	igen. Replace with configuration variables sim_igen_flags /
 	sim_m16_flags.

	* m16.igen: New file.  Copy mips16 insns here.
	* mips.igen: From here.

Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
 	to top.
	(tmp-igen, tmp-m16): Pass -I srcdir to igen.

Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>

	* gencode.c (build_instruction): Follow sim_write's lead in using
	BigEndianMem instead of !ByteSwapMem.

Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in (sim_gen): Dependent on target, select type of
 	generator.  Always select old style generator.

	configure: Re-generate.

	Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
 	targets.
	(SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
 	SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
 	IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
	(SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
 	SIM_@sim_gen@_*, set by autoconf.
	
Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.

	* interp.c (ColdReset): Remove #ifdef HASFPU, check
 	CURRENT_FLOATING_POINT instead.

	* interp.c (ifetch32): New function. Fetch 32 bit instruction.
	(address_translation): Raise exception InstructionFetch when
 	translation fails and isINSTRUCTION.
	
	* interp.c (sim_open, sim_write, sim_monitor, store_word,
 	sim_engine_run): Change type of of vaddr and paddr to
 	address_word.
	(address_translation, prefetch, load_memory, store_memory,
 	cache_op): Change type of vAddr and pAddr to address_word.

	* gencode.c (build_instruction): Change type of vaddr and paddr to
 	address_word.

Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
 	macro to obtain result of ALU op.

Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_info): Call profile_print.

Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_OBJS): Add sim-profile.o module.

	* sim-main.h (WITH_PROFILE): Do not define, defined in
 	common/sim-config.h.  Use sim-profile module.
	(simPROFILE): Delete defintion.

	* interp.c (PROFILE): Delete definition.
	(mips_option_handler): Delete 'p', 'y' and 'x' profile options.
	(sim_close): Delete code writing profile histogram.
	(mips_set_profile, mips_set_profile_size, writeout16, writeout32):
 	Delete.
	(sim_engine_run): Delete code profiling the PC.

Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.

	* interp.c (sim_monitor): Make register pointers of type
 	unsigned_word*.

	* sim-main.h: Make registers of type unsigned_word not
 	signed_word.

Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sync_operation): Rename from SyncOperation, make
 	global, add SD argument.
	(prefetch): Rename from Prefetch, make global, add SD argument.
	(decode_coproc): Make global.

	* sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.

	* gencode.c (build_instruction): Generate DecodeCoproc not
 	decode_coproc calls.

	* interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
	(SizeFGR): Move to sim-main.h
	(simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
 	simSIGINT, simJALDELAYSLOT): Move to sim-main.h
	(FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
 	sim-main.h.
	(FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
 	FP_RM_TOMINF, GETRM): Move to sim-main.h.
	(Uncached, CachedNoncoherent, CachedCoherent, Cached,
 	isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
	(UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
 	BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
	
	* sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
 	exception.
	(sim-alu.h): Include.
	(NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
 	(sim_cia): Typedef to instruction_address.
	
Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (interp.o): Rename generated file engine.c to
	oengine.c.
  	
	* interp.c: Update.
	
Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* gencode.c (build_instruction): Use FPR_STATE not fpr_state.
	
Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* gencode.c (build_instruction): For "FPSQRT", output correct
 	number of arguments to Recip.
	
Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (interp.o): Depends on sim-main.h

	* interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.

	* sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
 	ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
 	(REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
 	STATE, DSSTATE): Define
	(GPR, FGRIDX, ..): Define.

	* interp.c (registers, register_widths, fpr_state, ipc, dspc,
 	pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
	(GPR, FGRIDX, ...): Delete macros.
	
	* interp.c: Update names to match defines from sim-main.h
	
Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_monitor): Add SD argument.
	(sim_warning): Delete.  Replace calls with calls to
 	sim_io_eprintf.
	(sim_error): Delete. Replace calls with sim_io_error.
	(open_trace, writeout32, writeout16, getnum): Add SD argument.
	(mips_set_profile): Rename from sim_set_profile. Add SD argument.
	(mips_set_profile_size): Rename from sim_set_profile_size. Add SD
 	argument.
	(mips_size): Rename from sim_size. Add SD argument.

	* interp.c (simulator): Delete global variable.
	(callback): Delete global variable.
	(mips_option_handler, sim_open, sim_write, sim_read,
 	sim_store_register, sim_fetch_register, sim_info, sim_do_command,
 	sim_size,sim_monitor): Use sim_io_* not callback->*.
	(sim_open): ZALLOC simulator struct.
	(PROFILE): Do not define.

Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_open), support.h: Replace CHECKSIM macro found in
 	support.h with corresponding code.

	* sim-main.h (word64, uword64), support.h: Move definition to
 	sim-main.h.
	(WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.

	* support.h: Delete
	* Makefile.in: Update dependencies
	* interp.c: Do not include.
	
Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (address_translation, load_memory, store_memory,
 	cache_op): Rename to from AddressTranslation et.al., make global,
 	add SD argument
	
	* sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
 	CacheOp): Define.
	
	* interp.c (SignalException): Rename to signal_exception, make
 	global.

	* interp.c (Interrupt, ...): Move definitions to sim-main.h.
	
	* sim-main.h (SignalException, SignalExceptionInterrupt,
 	SignalExceptionInstructionFetch, SignalExceptionAddressStore,
 	SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
 	SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
 	Define.
  	
	* interp.c, support.h: Use.
	
Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
 	to value_fpr / store_fpr. Add SD argument.
	(NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
 	Multiply, Divide, Recip, SquareRoot, Convert): Make global.

	* sim-main.h (ValueFPR, StoreFPR): Define.
	
Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_engine_run): Check consistency between configure
 	WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
 	and HASFPU.

	* configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
        (mips_fpu): Configure WITH_FLOATING_POINT.
	(mips_endian): Configure WITH_TARGET_ENDIAN.
	* configure: Update.

Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>

	* configure: Regenerated.

Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>

	* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.

Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* gencode.c (print_igen_insn_models): Assume certain architectures
 	include all mips* instructions.
	(print_igen_insn_format): Use data_size==-1 as marker for MIPS16
 	instruction.

	* Makefile.in (tmp.igen): Add target. Generate igen input from
 	gencode file.

	* gencode.c (FEATURE_IGEN): Define.
	(main): Add --igen option.  Generate output in igen format.
	(process_instructions): Format output according to igen option.
	(print_igen_insn_format): New function.
	(print_igen_insn_models): New function.
	(process_instructions): Only issue warnings and ignore
 	instructions when no FEATURE_IGEN.

Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
 	MIPS targets.

Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
 	SIM_RESERVED_BITS): Delete, moved to common.
	(SIM_EXTRA_CFLAGS): Update.
	
Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure.in: Configure non-strict memory alignment.
	* configure: Regenerated to track ../common/aclocal.m4 changes.

Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>

	* gencode.c (SDBBP,DERET): Added (3900) insns.
	(RFE): Turn on for 3900.
	* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
	(dsstate): Made global.
	(SUBTARGET_R3900): Added.
	(CANCELDELAYSLOT): New.
	(SignalException): Ignore SystemCall rather than ignore and
	terminate.  Add DebugBreakPoint handling.
	(decode_coproc): New insns RFE, DERET; and new registers Debug
	and DEPC protected by SUBTARGET_R3900.
	(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
	bits explicitly.
	* Makefile.in,configure.in: Add mips subtarget option.
	* configure: Update.	

Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>

	* gencode.c: Add r3900 (tx39).
	

Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>

	* gencode.c (build_instruction): Don't need to subtract 4 for
	JALR, just 2.

Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>

	* interp.c: Correct some HASFPU problems.

Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (mips_options): Fix samples option short form, should
 	be `x'.

Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_info): Enable info code.  Was just returning.

Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (decode_coproc): Clarify warning about unsuported MTC0,
 	MFC0.

Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* gencode.c (build_instruction): Use SIGNED64 for 64 bit
 	constants.
	(build_instruction): Ditto for LL.

Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_open): Add call to sim_analyze_program, update
 	call to sim_config.

Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_kill): Delete.
	(sim_create_inferior): Add ABFD argument. Set PC from same.
	(sim_load): Move code initializing trap handlers from here.
	(sim_open): To here.
	(sim_load): Delete, use sim-hload.c.

	* Makefile.in (SIM_OBJS): Add sim-hload.o module.

Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_open): Add ABFD argument.
	(sim_load): Move call to sim_config from here.
	(sim_open): To here.  Check return status.

Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
 
 	* gencode.c (build_instruction): Two arg MADD should
 	not assign result to $0.
 
Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)

	* sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
	* sim/mips/configure.in: Regenerate.

Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>

	* interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
 	signed8, unsigned8 et.al. types.

	* interp.c (SUB_REG_FETCH): Handle both little and big endian
 	hosts when selecting subreg.

Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)

	* interp.c (sim_engine_run): Reset the ZERO register to zero
	regardless of FEATURE_WARN_ZERO.
	* gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.

Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (decode_coproc): Implement MTC0 N, CAUSE.
	(SignalException): For BreakPoints ignore any mode bits and just
 	save the PC.
	(SignalException): Always set the CAUSE register.

Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (SignalException): Clear the simDELAYSLOT flag when an
 	exception has been taken.

	* interp.c: Implement the ERET and mt/f sr instructions.

Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (SignalException): Don't bother restarting an
 	interrupt.

Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (SignalException): Really take an interrupt.
	(interrupt_event): Only deliver interrupts when enabled.

Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_info): Only print info when verbose.
	(sim_info) Use sim_io_printf for output.
	
Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (CoProcPresent): Add UNUSED attribute - not used by all
 	mips architectures.

Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_do_command): Check for common commands if a
 	simulator specific command fails.

Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>

	* interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
	and simBE when DEBUG is defined.

Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (interrupt_event): New function.  Pass exception event
 	onto exception handler.

	* configure.in: Check for stdlib.h.
	* configure: Regenerate.

	* gencode.c (build_instruction): Add UNUSED attribute to tempS
 	variable declaration.
	(build_instruction): Initialize memval1.
	(build_instruction): Add UNUSED attribute to byte, bigend,
 	reverse.
	(build_operands): Ditto.

	* interp.c: Fix GCC warnings.
	(sim_get_quit_code): Delete.

	* configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
	* Makefile.in: Ditto.
	* configure: Re-generate.
	
	* Makefile.in (SIM_OBJS): Add sim-watch.o module.

Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (mips_option_handler): New function parse argumes using
 	sim-options.
	(myname): Replace with STATE_MY_NAME.
	(sim_open): Delete check for host endianness - performed by
 	sim_config.
	(simHOSTBE, simBE): Delete, replaced by sim-endian flags.
	(sim_open): Move much of the initialization from here.
	(sim_load): To here.  After the image has been loaded and
 	endianness set.
	(sim_open): Move ColdReset from here.
	(sim_create_inferior): To here.
	(sim_open): Make FP check less dependant on host endianness.

	* Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
 	run.
	* interp.c (sim_set_callbacks): Delete.

	* interp.c (membank, membank_base, membank_size): Replace with
 	STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
	(sim_open): Remove call to callback->init. gdb/run do this.

	* interp.c: Update

	* sim-main.h (SIM_HAVE_FLATMEM): Define.

	* interp.c (big_endian_p): Delete, replaced by
 	current_target_byte_order.

Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (host_read_long, host_read_word, host_swap_word,
 	host_swap_long): Delete. Using common sim-endian.
	(sim_fetch_register, sim_store_register): Use H2T.
	(pipeline_ticks): Delete.  Handled by sim-events.
	(sim_info): Update.
	(sim_engine_run): Update.

Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_stop_reason): Move code determining simEXCEPTION
 	reason from here.
	(SignalException): To here. Signal using sim_engine_halt.
	(sim_stop_reason): Delete, moved to common.
	
Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>

	* interp.c (sim_open): Add callback argument.
	(sim_set_callbacks): Delete SIM_DESC argument.
	(sim_size): Ditto.

Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* Makefile.in (SIM_OBJS): Add common modules.

	* interp.c (sim_set_callbacks): Also set SD callback.
	(set_endianness, xfer_*, swap_*): Delete.
	(host_read_word, host_read_long, host_swap_word, host_swap_long):
 	Change to functions using sim-endian macros.
	(control_c, sim_stop): Delete, use common version.
	(simulate): Convert into.
	(sim_engine_run): This function.
	(sim_resume): Delete.
	
	* interp.c (simulation): New variable - the simulator object.
	(sim_kind): Delete global - merged into simulation.
	(sim_load): Cleanup.  Move PC assignment from here.
	(sim_create_inferior): To here.

	* sim-main.h: New file.
	* interp.c (sim-main.h): Include.
	
Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>

	* tconfig.in (SIM_HAVE_BIENDIAN): Define.

Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>

	* gencode.c (build_instruction): DIV instructions: check 
	for division by zero and integer overflow before using 
	host's division operation.

Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>

	* Makefile.in (SIM_OBJS): Add sim-load.o.
	* interp.c: #include bfd.h.
	(target_byte_order): Delete.
	(sim_kind, myname, big_endian_p): New static locals.
	(sim_open): Set sim_kind, myname.  Move call to set_endianness to
	after argument parsing.  Recognize -E arg, set endianness accordingly.
	(sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
	load file into simulator.  Set PC from bfd.
	(sim_create_inferior): Return SIM_RC.  Delete arg start_address.
	(set_endianness): Use big_endian_p instead of target_byte_order.

Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>

	* interp.c (sim_size): Delete prototype - conflicts with
 	definition in remote-sim.h.  Correct definition.

Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.
	* config.in: Ditto.

Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>

	* interp.c (sim_open): New arg `kind'.

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>

	* interp.c (sim_open): Set optind to 0 before calling getopt.

Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>

	* configure: Regenerated to track ../common/aclocal.m4 changes.

Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>

	* interp.c : Replace uses of pr_addr with pr_uword64
	where the bit length is always 64 independent of SIM_ADDR.
	(pr_uword64) : added.

Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>

	* configure: Re-generate.

Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>

	* configure: Regenerate to track ../common/aclocal.m4 changes.

Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>

	* interp.c (sim_open): New SIM_DESC result.  Argument is now
	in argv form.
	(other sim_*): New SIM_DESC argument.

Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>

	* interp.c: Fix printing of addresses for non-64-bit targets.
	(pr_addr): Add function to print address based on size.

Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>

	* interp.c (simopen): Add support for LSI MiniRISC PMON vectors.

Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>

	* gencode.c (build_mips16_operands): Correct computation of base
	address for extended PC relative instruction.

Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>

	* interp.c (mips16_entry): Add support for floating point cases.
	(SignalException): Pass floating point cases to mips16_entry.
	(ValueFPR): Don't restrict fmt_single and fmt_word to even
	registers.
	(StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
	or fmt_word.
	(COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
	and then set the state to fmt_uninterpreted.
	(COP_SW): Temporarily set the state to fmt_word while calling
	ValueFPR.

Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>

	* gencode.c (build_instruction): The high order may be set in the
	comparison flags at any ISA level, not just ISA 4.

Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>

	* Makefile.in (@COMMON_MAKEFILE_FRAG): Use
	COMMON_{PRE,POST}_CONFIG_FRAG instead.
	* configure.in: sinclude ../common/aclocal.m4.
	* configure: Regenerated.

Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>

	* configure: Rebuild after change to aclocal.m4.

Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)

	* configure configure.in Makefile.in:  Update to new configure
	scheme which is more compatible with WinGDB builds.
	* configure.in:  Improve comment on how to run autoconf.
	* configure:  Re-run autoconf to get new ../common/aclocal.m4.
	* Makefile.in:  Use autoconf substitution to install common
	makefile fragment.

Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>

	* gencode.c (build_instruction): Use BigEndianCPU instead of
	ByteSwapMem.

Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>

	* interp.c (sim_monitor): Make output to stdout visible in
	wingdb's I/O log window.

Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>

	* support.h: Undo previous change to SIGTRAP
	and SIGQUIT values.

Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>

	* interp.c (store_word, load_word): New static functions.
	(mips16_entry): New static function.
	(SignalException): Look for mips16 entry and exit instructions.
	(simulate): Use the correct index when setting fpr_state after
	doing a pending move.

Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>

	* interp.c: Fix byte-swapping code throughout to work on
	both little- and big-endian hosts.

Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>

	* support.h: Make definitions of SIGTRAP and SIGQUIT consistent
	with gdb/config/i386/xm-windows.h.

Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>

	* gencode.c (build_instruction): Work around MSVC++ code gen bug
	that messes up arithmetic shifts.

Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)

	* support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
	SIGTRAP and SIGQUIT for _WIN32.

Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>

	* gencode.c (build_instruction) [MUL]: Cast operands to word64, to
	force a 64 bit multiplication.
	(build_instruction) [OR]: In mips16 mode, don't do anything if the
	destination register is 0, since that is the default mips16 nop
	instruction.

Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>

	* gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
	(build_endian_shift): Don't check proc64.
	(build_instruction): Always set memval to uword64.  Cast op2 to
	uword64 when shifting it left in memory instructions.  Always use
	the same code for stores--don't special case proc64.

	* gencode.c (build_mips16_operands): Fix base PC value for PC
	relative operands.
	(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
	jal instruction.
	* interp.c (simJALDELAYSLOT): Define.
 	(JALDELAYSLOT): Define.
	(INDELAYSLOT, INJALDELAYSLOT): Define.
	(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.

Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)

	* interp.c (sim_open): add flush_cache as a PMON routine
	(sim_monitor): handle flush_cache by ignoring it

Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>

	* gencode.c (build_instruction): Use !ByteSwapMem instead of
	BigEndianMem.
	* interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
	(BigEndianMem): Rename to ByteSwapMem and change sense.
	(BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
	BigEndianMem references to !ByteSwapMem.
	(set_endianness): New function, with prototype.
	(sim_open): Call set_endianness.
	(sim_info): Use simBE instead of BigEndianMem.
	(xfer_direct_word, xfer_direct_long, swap_direct_word,
	swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
	xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
	ifdefs, keeping the prototype declaration.
	(swap_word): Rewrite correctly.
	(ColdReset): Delete references to CONFIG.  Delete endianness related
	code; moved to set_endianness.
	
Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>

	* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
	* interp.c (CHECKHILO): Define away.
	(simSIGINT): New macro.
	(membank_size): Increase from 1MB to 2MB.
	(control_c): New function.
	(sim_resume): Rename parameter signal to signal_number.  Add local
	variable prev.  Call signal before and after simulate.
	(sim_stop_reason): Add simSIGINT support.
	(sim_warning, sim_error, dotrace, SignalException): Define as stdarg
	functions always.
	(sim_warning): Delete call to SignalException.  Do call printf_filtered
	if logfh is NULL.
	(AddressTranslation): Add #ifdef DEBUG around debugging message and
	a call to sim_warning.

Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>

	* gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
	16 bit instructions.

Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>

	Add support for mips16 (16 bit MIPS implementation):
	* gencode.c (inst_type): Add mips16 instruction encoding types.
	(GETDATASIZEINSN): Define.
	(MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
	jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
	mtlo.
	(MIPS16_DECODE): New table, for mips16 instructions.
	(bitmap_val): New static function.
	(struct mips16_op): Define.
	(mips16_op_table): New table, for mips16 operands.
	(build_mips16_operands): New static function.
	(process_instructions): If PC is odd, decode a mips16
	instruction.  Break out instruction handling into new
	build_instruction function.
	(build_instruction): New static function, broken out of
	process_instructions.  Check modifiers rather than flags for SHIFT
	bit count and m[ft]{hi,lo} direction.
	(usage): Pass program name to fprintf.
	(main): Remove unused variable this_option_optind.  Change
	``*loptarg++'' to ``loptarg++''.
	(my_strtoul): Parenthesize && within ||.
	* interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
	(simulate): If PC is odd, fetch a 16 bit instruction, and
	increment PC by 2 rather than 4.
	* configure.in: Add case for mips16*-*-*.
	* configure: Rebuild.

Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>

	* interp.c: Allow -t to enable tracing in standalone simulator.
	Fix garbage output in trace file and error messages.

Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>

	* Makefile.in: Delete stuff moved to ../common/Make-common.in.
	(SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
	* configure.in: Simplify using macros in ../common/aclocal.m4.
	* configure: Regenerated.
	* tconfig.in: New file.

Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>

	* interp.c: Fix bugs in 64-bit port.
	Use ansi function declarations for msvc compiler.
	Initialize and test file pointer in trace code.
	Prevent duplicate definition of LAST_EMED_REGNUM.

Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>

	* interp.c (xfer_big_long): Prevent unwanted sign extension.

Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c (SignalException): Check for explicit terminating
 	breakpoint value.
	* gencode.c: Pass instruction value through SignalException()
 	calls for Trap, Breakpoint and Syscall.

Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
 	only used on those hosts that provide it.
	* configure.in: Add sqrt() to list of functions to be checked for.
	* config.in: Re-generated.
	* configure: Re-generated.

Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>

	* gencode.c (process_instructions): Call build_endian_shift when
	expanding STORE RIGHT, to fix swr.
	* support.h (SIGNEXTEND): If the sign bit is not set, explicitly
	clear the high bits.
	* interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
	Fix float to int conversions to produce signed values.

Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>

	* gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
	(process_instructions): Correct handling of nor instruction.
	Correct shift count for 32 bit shift instructions. Correct sign
	extension for arithmetic shifts to not shift the number of bits in
	the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
	unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
	Fix madd.
	* interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
	It's OK to have a mult follow a mult.  What's not OK is to have a
	mult follow an mfhi.
	(Convert): Comment out incorrect rounding code.

Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c (sim_monitor): Improved monitor printf
 	simulation. Tidied up simulator warnings, and added "--log" option
 	for directing warning message output.
	* gencode.c: Use sim_warning() rather than WARNING macro.

Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>

	* Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
	getopt1.o, rather than on gencode.c.  Link objects together.
	Don't link against -liberty.
	(gencode.o, getopt.o, getopt1.o): New targets.
	* gencode.c: Include <ctype.h> and "ansidecl.h".
	(AND): Undefine after including "ansidecl.h".
	(ULONG_MAX): Define if not defined.
	(OP_*): Don't define macros; now defined in opcode/mips.h.
	(main): Call my_strtoul rather than strtoul.
	(my_strtoul): New static function.

Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)

	* gencode.c (process_instructions):  Generate word64 and uword64
	instead of `long long' and `unsigned long long' data types.
	* interp.c:  #include sysdep.h to get signals, and define default
	for SIGBUS.
	* (Convert):  Work around for Visual-C++ compiler bug with type
	conversion.
	* support.h:  Make things compile under Visual-C++ by using
	__int64 instead of `long long'.  Change many refs to long long
	into word64/uword64 typedefs.

Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)

        * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
        INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
        (docdir): Removed.
        * configure.in (AC_PREREQ): autoconf 2.5 or higher.
        (AC_PROG_INSTALL): Added.
	(AC_PROG_CC): Moved to before configure.host call.
        * configure: Rebuilt.
	
Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* configure.in: Define @SIMCONF@ depending on mips target.
	* configure: Rebuild.
	* Makefile.in (run): Add @SIMCONF@ to control simulator
 	construction.
	* gencode.c: Change LOADDRMASK to 64bit memory model only.
	* interp.c: Remove some debugging, provide more detailed error
 	messages, update memory accesses to use LOADDRMASK.
	
Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>

	* configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
	AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
	stamp-h.
	* configure: Rebuild.
	* config.in: New file, generated by autoheader.
	* interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
	and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
	HAVE_ANINT and HAVE_AINT, as appropriate.
	* Makefile.in (run): Use @LIBS@ rather than -lm.
	(interp.o): Depend upon config.h.
	(Makefile): Just rebuild Makefile.
	(clean): Remove stamp-h.
	(mostlyclean): Make the same as clean, not as distclean.
	(config.h, stamp-h): New targets.

Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c (ColdReset): Fix boolean test. Make all simulator
 	globals static.

Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c (xfer_direct_word, xfer_direct_long,
	swap_direct_word, swap_direct_long, xfer_big_word,
	xfer_big_long, xfer_little_word, xfer_little_long,
	swap_word,swap_long): Added.
	* interp.c (ColdReset): Provide function indirection to
 	host<->simulated_target transfer routines.
	* interp.c (sim_store_register, sim_fetch_register): Updated to
 	make use of indirected transfer routines.

Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* gencode.c (process_instructions): Ensure FP ABS instruction
 	recognised.
	* interp.c (AbsoluteValue): Add routine. Also provide simple PMON
 	system call support.

Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c (sim_do_command): Complain if callback structure not
 	initialised.

Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c (Convert): Provide round-to-nearest and round-to-zero
 	support for Sun hosts.
	* Makefile.in (gencode): Ensure the host compiler and libraries
 	used for cross-hosted build.

Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* interp.c, gencode.c: Some more (TODO) tidying.

Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>

	* gencode.c, interp.c: Replaced explicit long long references with
 	WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
	* support.h (SET64LO, SET64HI): Macros added.

Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>

	* configure: Regenerate with autoconf 2.7.

Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>

	* interp.c (LoadMemory): Enclose text following #endif in /* */.
	* support.h: Remove superfluous "1" from #if.
	* support.h (CHECKSIM): Remove stray 'a' at end of line.

Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>

	* interp.c (StoreFPR): Control UndefinedResult() call on
 	WARN_RESULT manifest.

Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>

	* gencode.c: Tidied instruction decoding, and added FP instruction
 	support.

	* interp.c: Added dineroIII, and BSD profiling support. Also
 	run-time FP handling.

Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>

	* Changelog, Makefile.in, README.Cygnus, configure, configure.in,
 	gencode.c, interp.c, support.h: created.